linux - linux

	Commit message (Expand)	Author	Files	Lines
2017-04-12	clk: add clk_possible_parents debugfs file	Peter De Schrijver	1	-0/+32
2017-04-12	clk: imx: correct uart4_serial clock name in driver for i.MX6UL	Robin van der Gracht	1	-1/+1
2017-04-12	clk: zte: Mark pll config tables as const	Stephen Boyd	1	-2/+2
2017-04-12	clk: zte: add pll_vga clock for zx296718	Shawn Guo	1	-0/+24
2017-04-12	clk: zte: pd_bit is not 0 on zx296718	Shawn Guo	2	-2/+16
2017-04-12	clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks	Shawn Guo	1	-3/+3
2017-04-12	clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock	Robin van der Gracht	1	-4/+5
2017-04-12	cs-2000-cp: keep Reserved bit on each register	Kuninori Morimoto	1	-3/+22
2017-04-12	clk: qcom: msm8996: Fix the vfe1 powerdomain name	Rajendra Nayak	1	-1/+1
2017-04-12	clk: stm32f4: fix timeout management for pll and ready gate	Gabriel Fernandez	1	-14/+29
2017-04-12	clk: iproc: Remove redundant check	Ray Jui	1	-1/+1
2017-04-12	clk: stm32f4: fix: exclude values 0 and 1 for PLLQ	Gabriel Fernandez	1	-3/+10
2017-04-12	clk: hi6220: add debug APB clock	Leo Yan	2	-1/+5
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	1	-4/+4
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	4	-8/+27
2017-04-04	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid	1	-2/+4
2017-03-30	clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0	Geert Uytterhoeven	1	-11/+27
2017-03-30	clk: renesas: r8a7795: Add support for R-Car H3 ES2.0	Geert Uytterhoeven	1	-50/+151
2017-03-30	clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions	Geert Uytterhoeven	1	-0/+7
2017-03-30	clk: renesas: cpg-mssr: Add support for fixing up clock tables	Geert Uytterhoeven	2	-0/+72
2017-03-22	clk: rockchip: add pll_wait_lock for pll_enable	Elaine Zhang	1	-0/+3
2017-03-22	clk: rockchip: rename RK1108 to RV1108	Andy Yan	5	-226/+226
2017-03-22	dt-bindings: rk1108-cru: rename RK1108 to RV1108	Andy Yan	1	-6/+6
2017-03-21	clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0	Geert Uytterhoeven	1	-0/+24
2017-03-21	clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()	Geert Uytterhoeven	4	-4/+6
2017-03-21	clk: renesas: r8a7796: Reformat core clock table	Geert Uytterhoeven	1	-6/+6
2017-03-21	clk: renesas: r8a7795: Reformat core clock table	Geert Uytterhoeven	1	-10/+10
2017-03-21	clk: renesas: r8a7796: Correct name of watchdog clock	Geert Uytterhoeven	1	-1/+1
2017-03-21	clk: renesas: r8a7795: Correct name of watchdog clock	Geert Uytterhoeven	1	-1/+1
2017-03-21	clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs	Geert Uytterhoeven	1	-2/+2
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	2	-2/+2
2017-03-20	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver	1	-0/+2
2017-03-20	clk: tegra: Add SATA seq input control	Peter De Schrijver	2	-0/+26
2017-03-20	clk: tegra: Add Tegra210 special resets	Peter De Schrijver	2	-0/+98
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver	2	-197/+272
2017-03-20	clk: tegra: Implement reset control reset	Mikko Perttunen	1	-0/+16
2017-03-20	clk: tegra: Fix disable unused for clocks sharing enable bit	Peter De Schrijver	1	-0/+3
2017-03-20	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver	2	-0/+28
2017-03-20	clk: tegra: Add aclk	Peter De Schrijver	2	-0/+12
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver	2	-5/+89
2017-03-20	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver	3	-1/+28
2017-03-20	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver	2	-4/+4
2017-03-20	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver	4	-25/+81
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver	10	-4/+10
2017-03-20	clk: tegra: Fix type for m field	Peter De Schrijver	1	-1/+1
2017-03-20	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver	1	-1/+7
2017-03-20	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver	1	-6/+12
2017-03-20	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver	1	-5/+0
2017-03-20	clk: tegra: Correct afi clock parent	Peter De Schrijver	1	-1/+1
2017-03-20	clk: tegra: Fix ISP clock modelling	Peter De Schrijver	4	-4/+13