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* Merge tag 'char-misc-5.17-rc1' of ↵Linus Torvalds2022-01-1435-582/+4953
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the large set of char, misc, and other "small" driver subsystem changes for 5.17-rc1. Lots of different things are in here for char/misc drivers such as: - habanalabs driver updates - mei driver updates - lkdtm driver updates - vmw_vmci driver updates - android binder driver updates - other small char/misc driver updates Also smaller driver subsystems have also been updated, including: - fpga subsystem updates - iio subsystem updates - soundwire subsystem updates - extcon subsystem updates - gnss subsystem updates - phy subsystem updates - coresight subsystem updates - firmware subsystem updates - comedi subsystem updates - mhi subsystem updates - speakup subsystem updates - rapidio subsystem updates - spmi subsystem updates - virtual driver updates - counter subsystem updates Too many individual changes to summarize, the shortlog contains the full details. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (406 commits) counter: 104-quad-8: Fix use-after-free by quad8_irq_handler dt-bindings: mux: Document mux-states property dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC counter: remove old and now unused registration API counter: ti-eqep: Convert to new counter registration counter: stm32-lptimer-cnt: Convert to new counter registration counter: stm32-timer-cnt: Convert to new counter registration counter: microchip-tcb-capture: Convert to new counter registration counter: ftm-quaddec: Convert to new counter registration counter: intel-qep: Convert to new counter registration counter: interrupt-cnt: Convert to new counter registration counter: 104-quad-8: Convert to new counter registration counter: Update documentation for new counter registration functions counter: Provide alternative counter registration functions counter: stm32-timer-cnt: Convert to counter_priv() wrapper counter: stm32-lptimer-cnt: Convert to counter_priv() wrapper counter: ti-eqep: Convert to counter_priv() wrapper counter: ftm-quaddec: Convert to counter_priv() wrapper counter: intel-qep: Convert to counter_priv() wrapper counter: microchip-tcb-capture: Convert to counter_priv() wrapper ...
| * Merge tag 'phy-for-5.17' of ↵Greg Kroah-Hartman2021-12-3035-582/+4953
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.17 - New support: - Qualcomm eDP PHY driver - Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support - Lan966x ethernet serdes PHY driver - Support for uniphier NXI & Pro4 SoC - Qualcomm SM6350 USB2 support - Amlogic Meson8 HDMI TX PHY driver - Rockchip rk3568 usb2 support - Intel Thunder Bay eMMC PHY driver - Freescale IMX8 PCIe phy driver - Updates: - Cadence Sierra driver updates for multilink configurations - Bcm usb2 updates for Phy reg space * tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: cadence: Sierra: Add support for derived reference clock output dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add support to get SSC type from device tree dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names phy: cadence: Sierra: Prepare driver to add support for multilink configurations phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: mediatek: Fix missing check in mtk_mipi_tx_probe phy: uniphier-usb3ss: fix unintended writing zeros to PHY register phy: phy-mtk-tphy: use new io helpers to access register phy: phy-mtk-xsphy: use new io helpers to access register phy: mediatek: add helpers to update bits of registers ...
| | * phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade2021-12-271-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sierra has derived differential reference clock output which is sourced after the spread spectrum generation has been added. Add support to drive derived reference clock out of serdes. Model this derived clock as a "clock" so that platforms using this can enable it. Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz clock output. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade2021-12-271-1/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register sequences for PCIe + QSGMII PHY multilink configuration. PHY configuration for multi-link operation is done in two steps. e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. [1] For first step, the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. This will configure PHY registers associated for PCIe involving PLLLC registers and registers for first 2 lanes of PHY. [2] In second step, the register values are selected as [TYPE_QSGMII][TYPE_PCIE][ssc]. This will configure PHY registers associated for QSGMII involving PLLLC1 registers and registers for other 2 lanes of PHY. This completes the PHY configuration for multilink operation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade2021-12-271-8/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-13-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade2021-12-271-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix get_parent() callback to return the correct index of the parent for PLL_CMNLC1 clock. Add a separate table of register values corresponding to the parent index for PLL_CMNLC1. Update set_parent() callback accordingly. Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)") Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade2021-12-271-1/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-12-271-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-10-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade2021-12-271-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-9-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade2021-12-271-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade2021-12-271-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-7-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade2021-12-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade2021-12-271-56/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-3-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2021-12-271-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: mediatek: Fix missing check in mtk_mipi_tx_probeMiaoqian Lin2021-12-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The of_device_get_match_data() function may return NULL. Add check to prevent potential null dereference. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211224082103.7658-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-usb3ss: fix unintended writing zeros to PHY registerRyuta NAKANISHI2021-12-241-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to commit 4a90bbb478db ("phy: uniphier-pcie: Fix updating phy parameters"), in function uniphier_u3ssphy_set_param(), unintentionally write zeros to other fields when writing PHY registers. Fixes: 5ab43d0f8697 ("phy: socionext: add USB3 PHY driver for UniPhier SoC") Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1640150369-4134-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-mtk-tphy: use new io helpers to access registerChunfeng Yun2021-12-241-325/+179
| | | | | | | | | | | | | | | | | | | | | | | | Use new helpers mtk_phy_clear/set/update_bits() to access registers Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-mtk-xsphy: use new io helpers to access registerChunfeng Yun2021-12-241-94/+46
| | | | | | | | | | | | | | | | | | | | | | | | Use new helpers mtk_phy_clear/set/update_bits() to access registers Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: mediatek: add helpers to update bits of registersChunfeng Yun2021-12-241-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Add three helpers mtk_phy_clear/set/update_bits() for registers operation Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-mtk-tphy: add support efuse settingChunfeng Yun2021-12-241-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to some SoCs have a bit shift issue that will drop a bit for usb3 phy or pcie phy, fix it by adding software efuse reading and setting, but only support it optionally for version 2/3. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom-qmp: Add SM8450 PCIe1 PHY supportDmitry Baryshkov2021-12-242-0/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-rockchip-inno-usb2: add rk3568 supportPeter Geis2021-12-231-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rk3568 usb2phy is a standalone device with a single muxed interrupt. Add support for the registers to the usb2phy driver. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-rockchip-inno-usb2: support muxed interruptsPeter Geis2021-12-231-49/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rk3568 usb2phy has a single muxed interrupt that handles all interrupts. Allow the driver to plug in only a single interrupt as necessary. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-rockchip-inno-usb2: support standalone phy nodesPeter Geis2021-12-231-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Rockchip devices have the usb2 phy devices as standalone nodes instead of children of the grf node. Allow the driver to find the grf node from a phandle. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-rockchip-inno-usb2: support #address_cells = 2Peter Geis2021-12-231-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom-qmp: Add SM8450 PCIe0 PHY supportDmitry Baryshkov2021-12-182-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom-qmp: Add SM8450 USB QMP PHYsVinod Koul2021-12-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the USB DP & UNI PHYs found on SM8450. This is same as the phy version used on SM8350 and sequences turned out to be same, so use the same table from SM8350 for this as well. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213131450.535775-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: freescale: pcie: explicitly add bitfield.hVinod Koul2021-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kernel test robot complains about missing FIELD_PREP, so include bitfield.h for that drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:37: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] Reported-by: kernel test robot <lkp@intel.com> Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Link: https://lore.kernel.org/r/20211215060834.921617-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: freescale: pcie: Initialize the imx8 pcie standalone phy driverRichard Zhu2021-12-143-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Link: https://lore.kernel.org/r/1638432158-4119-6-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: rockchip-inno-usb2: remove redundant assignment to variable delayColin Ian King2021-12-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable delay is being assigned to zero and the code falls through to the next case in a switch statement that returns out of the function. The variable is never read in this scenario and so the assignment is redundant and can be removed. Cleans up scan-build static analysis warning: drivers/phy/rockchip/phy-rockchip-inno-usb2.c:753:3: warning: Value stored to 'delay' is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20211211180054.525368-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: lan966x: Remove set_speed functionHoratiu Vultur2021-12-141-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the set_speed function and allow the driver to figure out the speed at which needs to configure the serdes based on the interface type. Fixes: 305524902a0045 ("phy: Add lan966x ethernet serdes PHY driver") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211211214717.1284306-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: ti: Use IS_ERR_OR_NULL() to clean codeMiaoqian Lin2021-12-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20211212142226.23674-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: tegra: xusb: Fix return value of tegra_xusb_find_port_node functionMiaoqian Lin2021-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | callers of tegra_xusb_find_port_node() function only do NULL checking for the return value. return NULL instead of ERR_PTR(-ENOMEM) to keep consistent. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20211213020507.1458-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom: use struct_size instead of sizeofGuo Zhengkui2021-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use struct_size() to get the accurate size of `clk_hw_onecell_data` with a variable size array, instead of sizeof(data) to get the size of a pointer. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211209032114.9416-1-guozhengkui@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom-qmp: Add SM8450 UFS QMP PhyVinod Koul2021-12-071-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SM8450 UFS seems to use same sequence as SM8350, so reuse the sequence from SM8450. Add the new clock list for this phy and the new compatible Signed-off-by: Vinod Koul <vkoul@kernel.org> Co-developed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Link: https://lore.kernel.org/r/20211201074456.3969849-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: lan966x: Extend lan966x to support multiple phy interfaces.Horatiu Vultur2021-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the driver is supporting only the interfaces QSGMII, SGMII, RGMII and GMII. This patch extend the supported interfaces with 1000BASE-X and 2500BASE-X. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20211130101015.164916-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: intel: Remove redundant dev_err call in thunderbay_emmc_phy_probe()Zou Wei2021-12-021-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1637822289-24534-1-git-send-email-zou_wei@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: stm32: adopt dev_err_probe for regulatorsFabrice Gasnier2021-11-261-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change stm32-usbphyc driver to use dev_err_probe(), to benefit of devices_deferred debugfs in case of probe deferral. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/1635172265-26219-1-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: bcm-ns-usb2: improve printing ref clk errorsRafał Miłecki2021-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve message & use dev_err_probe() helper which prints actual error (helpful for debugging) and deals with -EPROBE_DEFER. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211123221521.25323-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: intel: Add Thunder Bay eMMC PHY supportRashmi A2021-11-233-0/+522
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of eMMC PHY for Intel Thunder Bay SoC, uses the Arasan eMMC phy Signed-off-by: Rashmi A <rashmi.a@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211027115516.4475-5-rashmi.a@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: Add lan966x ethernet serdes PHY driverHoratiu Vultur2021-11-234-0/+766
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Microchip lan966x ethernet serdes PHY driver for interfaces available in the lan966x SoC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211116100818.1615762-4-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: phy-can-transceiver: Make devm_gpiod_get optionalAswath Govindraju2021-11-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the standby/enable gpio can be pulled low/high and would not be connected to a gpio. The current driver implementation will return an error in these cases. Therefore, make devm_gpiod_get optional. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20211102112120.23637-1-a-govindraju@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: cadence-torrent: use swap() to make code cleanerYang Guang2021-11-231-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the macro 'swap()' defined in 'include/linux/minmax.h' to avoid opencoding it. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Yang Guang <yang.guang5@zte.com.cn> Link: https://lore.kernel.org/r/20211104065233.1833499-1-yang.guang5@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-ahci: Add support for Pro4 SoCKunihiko Hayashi2021-11-232-5/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PHY interface built into ahci controller implemented in UniPhier Pro4 SoC. Pro4 SoC distinguishes it from other SoCs as "legacy" SoC, which has GIO clock line. And Pro4 AHCI-PHY needs to control additional reset lines ("pm", "tx", and "rx"). Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-9-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-pcie: Add dual-phy support for NX1 SoCKunihiko Hayashi2021-11-231-14/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate configuration values to both PHY registers. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-7-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-pcie: Set VCOPLL clamp mode in PHY registerKunihiko Hayashi2021-11-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoCKunihiko Hayashi2021-11-231-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for UniPhier NX1 SoC. This includes a compatible string, SoC-dependent data, and a function that set to 2-lane mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-5-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: uniphier-usb3: Add compatible string for NX1 SoCKunihiko Hayashi2021-11-232-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for UniPhier NX1 SoC. This includes a compatible string and the same SoC-dependent data as LD20/PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: amlogic: Add a new driver for the HDMI TX PHY on Meson8/8b/8m2Martin Blumenstingl2021-11-233-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amlogic Meson8/8b/8m2 have a built-in HDMI PHY in the HHI register region. Unfortunately only few register bits are documented. For HHI_HDMI_PHY_CNTL0 the magic numbers are taken from the 3.10 vendor kernel. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211020195107.1564533-3-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| | * phy: qcom: Introduce new eDP PHY driverBjorn Andersson2021-11-234-0/+686
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many recent Qualcomm platforms comes with native DP and eDP support. This consists of a controller in the MDSS and a QMP-like PHY. While similar to the well known QMP block, the eDP PHY only has TX lanes and the programming sequences are slightly different. Rather than continuing the trend of parameterize the QMP driver to pieces, this introduces the support as a new driver. The registration of link and pixel clocks are borrowed from the QMP driver. The non-DP link frequencies are omitted for now. The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only the prior is supported for now. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20211103234410.1352424-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 21:22:54 +0100