summaryrefslogtreecommitdiffstats
path: root/drivers/phy (follow)
Commit message (Expand)AuthorAgeFilesLines
* phy: Revert "phy: ti: j721e-wiz: add missing of_node_put"Vinod Koul2021-04-161-1/+0
* phy: ti: j721e-wiz: Add missing include linux/slab.hShixin Liu2021-04-161-0/+1
* phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove()Yang Yingliang2021-04-161-1/+1
* phy: fix resource_size.cocci warningskernel test robot2021-04-061-1/+1
* phy: Sparx5 Eth SerDes: Use direct register operationsSteen Hegelund2021-04-061-918/+951
* phy: hisilicon: Use the correct HiSilicon copyrightHao Fang2021-04-062-2/+2
* phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMONRandy Dunlap2021-04-061-1/+1
* phy: qcom-qmp: add support for sm8250-usb3-dp phyDmitry Baryshkov2021-03-312-22/+412
* phy: qcom-qmp: rename common registersDmitry Baryshkov2021-03-312-43/+44
* phy: qcom-qmp: move DP functions to callbacksDmitry Baryshkov2021-03-311-22/+51
* phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMIIKishon Vijay Abraham I2021-03-311-0/+2
* phy: zynqmp: Handle the clock enable/disable properlyManish Narani2021-03-311-7/+51
* phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5Geert Uytterhoeven2021-03-311-0/+1
* phy: cadence-torrent: Add delay for PIPE clock to be stableKishon Vijay Abraham I2021-03-311-0/+9
* phy: cadence-torrent: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-1/+1
* phy: cadence-torrent: Do not configure SERDES if it's already configuredKishon Vijay Abraham I2021-03-311-10/+22
* phy: cadence-torrent: Group reset APIs and clock APIsKishon Vijay Abraham I2021-03-311-31/+53
* phy: ti: j721e-wiz: Do not configure wiz if its already configuredFaiz Abbas2021-03-311-5/+16
* phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I2021-03-311-3/+37
* phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I2021-03-312-3/+265
* phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I2021-03-311-0/+3
* phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I2021-03-311-10/+15
* phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I2021-03-311-1/+1
* phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-2/+2
* phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I2021-03-311-11/+25
* phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I2021-03-311-22/+35
* phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnodeKishon Vijay Abraham I2021-03-311-0/+4
* phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I2021-03-311-0/+4
* phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()Kishon Vijay Abraham I2021-03-311-10/+7
* phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I2021-03-311-1/+6
* phy: qcom-qmp: add hbr3_hbr2 voltage and premphasis swing tableKuogee Hsieh2021-03-301-2/+21
* phy: ingenic: Fix a typo in ingenic_usb_phy_probe()Wei Yongjun2021-03-301-2/+2
* phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()Wei Yongjun2021-03-301-2/+2
* phy: marvell: ARMADA375_USBCLUSTER_PHY should not default to y, unconditionallyGeert Uytterhoeven2021-03-301-2/+2
* phy: ti: j721e-wiz: add missing call to of_node_put()Yang Li2021-03-301-0/+1
* phy: ralink: phy-mt7621-pci: fix XTAL bitmaskSergio Paracuellos2021-03-301-1/+1
* phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade2021-03-301-16/+31
* phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TIKishon Vijay Abraham I2021-03-301-14/+44
* phy: ti: j721e-wiz: Add support for configuring QSGMIIKishon Vijay Abraham I2021-03-301-2/+62
* phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clockSwapnil Jakhade2021-03-301-28/+49
* phy: cadence-torrent: Add support to drive refclk outKishon Vijay Abraham I2021-03-302-3/+186
* phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>Kishon Vijay Abraham I2021-03-301-0/+89
* phy: ti: j721e-wiz: Model the internal clocks without device tree inputKishon Vijay Abraham I2021-03-301-5/+139
* phy: ti: j721e-wiz: Configure full rate divider for AM64Kishon Vijay Abraham I2021-03-301-3/+36
* phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanupKishon Vijay Abraham I2021-03-301-0/+6
* phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_selKishon Vijay Abraham I2021-03-301-41/+34
* drivers: phy: add support for Armada CP110 UTMI PHYKonstantin Porotchkin2021-03-303-0/+393
* phy: qualcomm: remove duplicate argumentZhang Yunkai2021-03-251-2/+2
* phy: intel: Fix a typoBhaskar Chowdhury2021-03-251-1/+1
* phy: Add Sparx5 ethernet serdes PHY driverSteen Hegelund2021-03-177-0/+5331
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 22:30:16 +0100