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* pinctrl: Add core support for Aspeed SoCsAndrew Jeffery2016-09-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: as3722: convert PINCTRL_AS3722 from bool to tristatePaul Gortmaker2016-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: config PINCTRL_AS3722 bool "Pinctrl and GPIO driver for ams AS3722 PMIC" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: palmas: convert PINCTRL_PALMAS from bool to tristatePaul Gortmaker2016-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: config PINCTRL_PALMAS bool "Pinctrl driver for the PALMAS Series MFD devices" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: max77620: select PINMUXArnd Bergmann2016-06-151-0/+1
| | | | | | | | | | | | | | | | The recently added max77620 driver fails to build when CONFIG_PINMUX is not set: pinctrl/pinctrl-max77620.c:272:21: error: variable 'max77620_pinmux_ops' has initializer but incomplete type static const struct pinmux_ops max77620_pinmux_ops = { ^~~~~~~~~~ pinctrl/pinctrl-max77620.c:273:2: error: unknown field 'get_functions_count' specified in initializer This adds the Kconfig 'select' statement that was clearly meant to be there and is used in all other pinmux drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024Laxman Dewangan2016-05-301-0/+10
| | | | | | | | | | | | | | MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins which also act as the special function in alternate mode. Also there is configuration like push-pull, open drain, FPS timing etc for these pins. Add pin control driver to configure these parameters through pin control APIs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driverNeil Armstrong2016-05-301-0/+11
| | | | | | | | Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Turn AMD support to tristateJean Delvare2016-02-161-1/+1
| | | | | | | | | The pinctrl-amd driver builds just fine as a module so give users this option. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-pic32: Add PIC32 pin control driverJoshua Henderson2016-02-051-0/+17
| | | | | | | | | | | | Add a driver for the pin controller present on the Microchip PIC32 including the specific variant PIC32MZDA. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: move Tegra pinctrl drivers to sub-directoryMasahiro Yamada2016-02-051-31/+1
| | | | | | | | | Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add STM32 MCUs supportMaxime Coquelin2016-01-271-0/+1
| | | | | | | | | | | | This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v4.4-rc5' into develLinus Walleij2015-12-171-4/+0
|\ | | | | | | Linux 4.4-rc5
| * pinctrl: remove redundant if conditional from KconfigMasahiro Yamada2015-11-171-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole menu is guarded by menu "Pin controllers" depends on PINCTRL ... endmenu The if conditional outside of it is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: activate pxa architectureRobert Jarzmik2015-12-101-0/+1
| | | | | | | | | | | | | | | | As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: fix a typo in KconfigMasahiro Yamada2015-12-011-1/+1
|/ | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: introduce driver for Atmel PIO4 controllerLudovic Desroches2015-09-211-0/+13
| | | | | | | | Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2 chip family. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: driver for Conexant Digicolor CX92755 pin mappingBaruch Siach2015-07-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This adds pinctrl and gpio driver to the CX92755 SoC "General Purpose Pin Mapping" hardware block. The CX92755 is one SoC from the Conexant Digicolor series. Pin mapping hardware supports configuring pins as either GPIO, or up to 3 other "client select" functions. This driver adds support for pin muxing using the generic device tree binding, and a basic gpiolib driver for the GPIO functionality. This driver does not currently support GPIO interrupts, and pad configuration. v2: * Address review comments for Linus Walleij: - Add a pointer to pinctrl_desc in struct dc_pinmap - Drop the now redundant pinctrl_pin_desc field - Adapt dc_get_group_{name,pins} to these changes, and add a comment explaining the 1-to-1 pin-groups relation * Staticise dc_pmxops * Protect the GP_CLIENTSEL clct parameter with parenthesis Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier pinctrl core supportMasahiro Yamada2015-07-161-0/+1
| | | | | | | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Changes in v2: - drop vogus THIS_MODULE because this file is always built-in - drop vogus "include <linux/module.h> because this file is always built-in Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sirf: add sirf atlas7 pinctrl and gpio supportWei Chen2015-05-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add Pistachio SoC pin control driverAndrew Bresticker2015-05-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the pin controller present on the IMG Pistachio SoC. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Changes from v4: - Switched to using gpiochip_add_pin_range(). - Fixed up Kconfig entry. Changes from v3: - Addressed review comments from Ezequiel. Changes from v2: - Removed module stuff which would be compiled out. Changes from v1: - Addressed review comments from Linus. - Changed compatible string to "img,pistachio-system-pinctrl". - Look for GPIO sub-nodes by name. - A couple of bug fixes. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Kevin Cernekee <cernekee@chromium.org> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add lpc18xx pinctrl driverJoachim Eastwood2015-05-061-0/+9
| | | | | | | | | | | Pinctrl driver for the System Control Unit (SCU) found on NXP LPC18xx/43xx devices. Driver uses the generic pinctrl DT bindings for multiplexing and property settings. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix allmodconfig noiseLinus Walleij2015-04-151-1/+4
| | | | | | | | There was some mess in the dependencies in the pinctrl Kconfig for compile tests under allmodconfig. Mea Culpa. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add AMD GPIO driver support.Ken Xue2015-03-181-0/+15
| | | | | | | | | KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.Hongzhou Yang2015-03-181-0/+1
| | | | | | | | | | | | | The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: bcm: consolidate Broadcom pinctrl driversRay Jui2015-03-181-18/+1
| | | | | | | Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: add a driver for Tegra210Stephen Warren2015-03-091-0/+4
| | | | | | | | | | Tegra210's pinmux supports a different set of pins/options than earlier SoCs, so requires its own driver (well, table of pin-specific data). Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add driver for Amlogic Meson SoCsBeniamino Galvani2015-01-261-0/+8
| | | | | | | | | | | | | This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sirf: drop marco supportBarry Song2015-01-141-1/+1
| | | | | | | marco chip has been dropped, clear its support. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add driver for ZynqSoren Brinkmann2015-01-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a pin-control driver for Zynq. Changes since v2: - driver-specific DT properties are passed to the core in two arrays, one for the actual DT parsing one for the debugfs representation. Issue a compiler warning when the number of entries is not the same for both arrays. Changes since v1: - fix EMIO_SD1_CD pin name - add USB to pinmux options changes since RFCv2: - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is present in DT but no driver available. - add #defines to get rid of magical constants - add commas at end of initializers - separate changes in mach-zynq in separate patch - add driver specific io-standard DT property - refactored pinconf set function to not require arguments for argument-less properties - squash other patches in - support for IO-standard property - support for low-power mode property - migration to pinconf_generic_dt_node_to_map_all() - use newly created infrastructure to add pass driver-specific DT params to pinconf-generic changes since RFC: - use syscon/regmap to access registers in SLCR space - rebase to 3.18: rename enable -> set_mux - add kernel-doc - support pinconf - supported attributes - pin-bias: pull up, tristate, disable - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display argument Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Move Intel Baytrail pinctrl driver under intel directoryMika Westerberg2014-10-291-12/+1
| | | | | | | | We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'gpio-v3.18-1' of ↵Linus Torvalds2014-10-091-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO changes from Linus Walleij: "This is the bulk of GPIO changes for the v3.18 development cycle: - Increase the default ARCH_NR_GPIO from 256 to 512. This was done to avoid having a custom <asm/gpio.h> header for the x86 architecture - GPIO is custom and complicated enough as it is already! We want to move to a radix to store the descriptors going forward, and finally get rid of this fixed array size altogether. - Endgame patching of the gpio_remove() semantics initiated by Abdoulaye Berthe. It is not accepted by the system that the removal of a GPIO chip fails during eg reboot or shutdown, and therefore the return value has now painfully been refactored away. For special cases like GPIO expanders on a hot-pluggable bus like USB, we may later add some gpiochip_try_remove() call, but for the cases we have now, return values are moot. - Some incremental refactoring of the gpiolib core and ACPI GPIO library for more descriptor usage. - Refactor the chained IRQ handler set-up method to handle also threaded, nested interrupts and set up the parent IRQ correctly. Switch STMPE and TC3589x drivers to use this registration method. - Add a .irq_not_threaded flag to the struct gpio_chip, so that also GPIO expanders that block but are still not using threaded IRQ handlers. - New drivers for the ARM64 X-Gene SoC GPIO controller. - The syscon GPIO driver has been improved to handle the "DSP GPIO" found on the TI Keystone 2 SoC:s. - ADNP driver switched to use gpiolib irqchip helpers. - Refactor the DWAPB driver to support being instantiated from and MFD cell (platform device). - Incremental feature improvement in the Zynq, MCP23S08, DWAPB, OMAP, Xilinx and Crystalcove drivers. - Various minor fixes" * tag 'gpio-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (52 commits) gpio: pch: Build context save/restore only for PM pinctrl: abx500: get rid of unused variable gpio: ks8695: fix 'else should follow close brace '}'' gpio: stmpe: add verbose debug code gpio: stmpe: fix up interrupt enable logic gpio: staticize xway_stp_init() gpio: handle also nested irqchips in the chained handler set-up gpio: set parent irq on chained handlers gpiolib: irqchip: use irq_find_mapping while removing irqchip gpio: crystalcove: support virtual GPIO pinctrl: bcm281xx: make Kconfig dependency more strict gpio: kona: enable only on BCM_MOBILE or for compile testing gpio, bcm-kona, LLVMLinux: Remove use of __initconst gpio: Fix ngpio in gpio-xilinx driver gpio: dwapb: fix pointer to integer cast gpio: xgene: Remove unneeded #ifdef CONFIG_OF guard gpio: xgene: Remove unneeded forward declation for struct xgene_gpio gpio: xgene: Fix missing spin_lock_init() gpio: ks8695: fix switch case indentation gpiolib: add irq_not_threaded flag to gpio_chip ...
| * pinctrl: bcm281xx: make Kconfig dependency more strictUwe Kleine-König2014-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | This driver is only useful on BCM281xx, so let the driver depend on ARCH_BCM_MOBILE but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx/mxs: move freescale drivers to subdirLinus Walleij2014-09-041-109/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves all the Freescale-related drivers (i.MX and MXS) to its own subdirectory to clear the view. Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Anson Huang <b20788@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Denis Carikli <denis@eukrea.com> Cc: Markus Pargmann <mpa@pengutronix.de> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add i.MX21 pincontrol driverAlexander Shiyan2014-08-281-0/+7
|/ | | | | | | | This patch adds pincontrol driver for Freescale i.MX21 SOCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'dt-for-3.17' of ↵Linus Torvalds2014-08-081-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree changes from Olof Johansson: "Unlike the board branch, this keeps having large sets of changes for every release, but that's quite expected and is so far working well. Most of this is plumbing for various device bindings and new platforms, but there's also a bit of cleanup and code removal for things that are moved from platform code to DT contents (some OMAP clock code in particular). There's also a pinctrl driver for tegra here (appropriately acked), that's introduced this way to make it more bisectable. I'm happy to say that there were no conflicts at all with this branch this release, which means that changes are flowing through our tree as expected instead of merged through driver maintainers (or at least not done with conflicts). There are several new boards added, and a couple of SoCs. In no particular order: - Rockchip RK3288 SoC support, including DTS for a dev board that they have seeded with some community developers. - Better support for Hardkernel Exynos4-based ODROID boards. - CCF conversions (and dtsi contents) for several Renesas platforms. - Gumstix Pepper (TI AM335x) board support - TI eval board support for AM437x - Allwinner A23 SoC, very similar to existing ones which mostly has resulted in DT changes for support. Also includes support for an Ippo tablet with the chipset. - Allwinner A31 Hummingbird board support, not to be confused with the SolidRun i.MX-based Hummingboard. - Tegra30 Apalis board support" * tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits) ARM: dts: Enable USB host0 (EHCI) on rk3288-evb ARM: dts: add rk3288 ehci usb devices ARM: dts: Turn on USB host vbus on rk3288-evb ARM: tegra: apalis t30: fix device tree compatible node ARM: tegra: paz00: Fix some indentation inconsistencies ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: dts: rockchip: add watchdog node ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 ARM: dts: Add missing pinctrl for uart0/1 for exynos3250 ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250 ARM: dts: Add TMU dt node to monitor the temperature for exynos3250 ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250 ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only ARM: dts: max77686 is exynos5250-snow only ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table ARM: dts: Add PMU DT node for exynos5260 SoC ARM: EXYNOS: Add support for Exynos5410 PMU ARM: dts: Add PMU to exynos5410 ...
| * pinctrl: Add NVIDIA Tegra XUSB pad controller supportThierry Reding2014-07-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads that lanes can be assigned to in order to support a variety of interface options: USB 2.0, USB 3.0, PCIe and SATA. In addition to the pin controller used to assign lanes to pads two PHYs are exposed to allow the bricks for PCIe and SATA to be powered up and down by PCIe and SATA drivers. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | pinctrl: baytrail: Convert to use gpiolib irqchipMika Westerberg2014-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | Instead of open-coding irqchip handling in the driver we can take advantage of the new irqchip helpers provided by the gpiolib core. While doing this we also make sure that we call gpiochip_irqchip_add() after the gpiochip itself is registered as required. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: move all Nomadik drivers to subdirLinus Walleij2014-07-111-44/+1
| | | | | | | | | | | | | | We have a bunch of Nomadik family pin control drivers, so let's move them into their own subdirectory. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: samsung: Group all drivers in a sub-dirSachin Kamat2014-07-111-26/+1
| | | | | | | | | | | | | | | | Group all pin control drivers of Samsung platform together in a sub-directory for easy maintenance. Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: msm: move all qualcomm drivers to subdirLinus Walleij2014-07-111-39/+1
| | | | | | | | | | | | | | | | | | | | We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: msm: Add msm8960 definitionsBjorn Andersson2014-07-111-0/+8
| | | | | | | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add i.MX1 pincontrol driverAlexander Shiyan2014-07-111-0/+7
| | | | | | | | | | | | | | | | This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONFUwe Kleine-König2014-07-111-2/+2
|/ | | | | | | | | | These symbols are supposed to be selected by the drivers actually needing them. The only situation where it would make sense to enable them without a driver selecting them is when an out-of-tree pinctrl driver is used or for compile testing. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add pinctrl driver for imx6sxAnson Huang2014-05-271-0/+7
| | | | | | | | | Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: switch to using generic GPIO irqchip helpersLinus Walleij2014-05-231-0/+1
| | | | | | | | | | This switches the Qualcomm MSM pin control driver over to using the generic GPIO irqchip helpers. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCsAntoine Tenart2014-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: use regmaps instead of raw mappingsHeiko Stübner2014-05-091-0/+1
| | | | | | | | This allows us to use syscons in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directoryMaxime Ripard2014-05-041-5/+1
| | | | | | | This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* pinctrl: sirf: switch driver to use gpiolib irqchip helpersLinus Walleij2014-04-231-0/+1
| | | | | | | | This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Add definitions for IPQ8064Andy Gross2014-04-231-0/+8
| | | | | | | | | This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/at91: convert driver to use gpiolib irqchipAlexander Stein2014-04-221-0/+3
| | | | | | | | | This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>