| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | pinctrl-aspeed-g5: Never set SCU90[6] | Andrew Jeffery | 2016-11-07 | 1 | -1/+1 |
| * | pinctrl: aspeed-g5: Fix pin association of SPI1 function | Andrew Jeffery | 2016-10-18 | 1 | -8/+78 |
| * | pinctrl: aspeed-g5: Fix GPIOE1 typo | Andrew Jeffery | 2016-10-18 | 1 | -1/+1 |
| * | pinctrl: aspeed-g5: Fix names of GPID2 pins | Andrew Jeffery | 2016-10-18 | 1 | -6/+6 |
| * | pinctrl: aspeed: "Not enabled" is a significant mux state | Andrew Jeffery | 2016-10-18 | 1 | -5/+7 |
| * | pinctrl: aspeed: fix regmap error handling | Arnd Bergmann | 2016-09-13 | 1 | -3/+3 |
| * | pinctrl: Add pinctrl-aspeed-g5 driver | Andrew Jeffery | 2016-09-07 | 3 | -0/+817 |
| * | pinctrl: Add pinctrl-aspeed-g4 driver | Andrew Jeffery | 2016-09-07 | 3 | -0/+1240 |
| * | pinctrl: Add core support for Aspeed SoCs | Andrew Jeffery | 2016-09-07 | 4 | -0/+1079 |
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