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* Merge tag 'v5.5-rc3' into develLinus Walleij2019-12-291-16/+8
|\ | | | | | | Linux 5.5-rc3
| * pinctrl: aspeed-g6: Fix LPC/eSPI mux configurationAndrew Jeffery2019-12-121-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Early revisions of the AST2600 datasheet are conflicted about the state of the LPC/eSPI strapping bit (SCU510[6]). Conversations with ASPEED determined that the reference pinmux configuration tables were in error and the SCU documentation contained the correct configuration. Update the driver to reflect the state described in the SCU documentation. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202050110.15340-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed-g6: Add AST2600 pinconf supportJohnny Huang2019-12-132-0/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Use masks to describe pinconf bitfieldsJohnny Huang2019-12-134-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Move aspeed_pin_config_map to separate source fileJohnny Huang2019-12-134-33/+44
| | | | | | | | | | | | | | | | | | | | | | The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Add ASPEED_SB_PINCONF() helperJohnny Huang2019-12-133-181/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed-g6: Add support for the AST2600 USB pinmuxJohnny Huang2019-12-132-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 has two USB ports, A, B: Port A supports 4 distinct modes: 1. PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux configJohnny Huang2019-12-131-1/+29
|/ | | | | | | | | | | These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groupsJohnny Huang2019-10-162-40/+33
| | | | | | | | | | | | AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Fix UART13 group pinmuxJohnny Huang2019-10-161-2/+2
| | | | | | | | | | | | | When UART13G1 is set the pinmux configuration in SCU4B8 for UART13G0 should be cleared. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-7-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitivelyAndrew Jeffery2019-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | Signal descriptors can represent multi-bit bitfields and so have explicit "enable" and "disable" states. However many descriptor instances only describe a single bit, and so the SIG_DESC_SET() macro is provides an abstraction for the single-bit cases: Its expansion configures the "enable" state to set the bit and "disable" to clear. SIG_DESC_CLEAR() was introduced to provide a similar single-bit abstraction for for descriptors to clear the bit of interest. However its behaviour was defined as the literal inverse of SIG_DESC_SET() - the impact is the bit of interest is set in the disable path. This behaviour isn't intuitive and doesn't align with how we want to use the macro in practice, so make it clear the bit for both the enable and disable paths. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-6-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configurationJohnny Huang2019-10-161-16/+8
| | | | | | | | | | | | | The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially unclear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, resolve rebase conflicts] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-5-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Fix I2C14 SDA descriptionAndrew Jeffery2019-10-161-1/+1
| | | | | | | | | | | | | The I2C function the pin participated in was incorrectly named SDA14 which lead to a failure to mux: [ 6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-4-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g6: Sort pins for sanityAndrew Jeffery2019-10-161-11/+11
| | | | | | | | | Some pins crept in that weren't ordered in the list. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.4-1' of ↵Linus Torvalds2019-09-196-1802/+4523
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.4 kernel cycle: Core changes: - Fix errors in example code in the documentation. New drivers: - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the Ingenic driver. - Support Cirrus Logic Madera CS47L92 and CS47L15. - Support Allwinner Sunxi V3S. - Support Aspeed 2600 BMC. - Support Qualcomm SC7180. - Support Marvell MVEBU CS115. Driver improvements: - Clean up a few drivers to use the devm_platform_ioremap_resource() helper. - Pass the irqchip when registering the gpio_chip in some pin controllers that are also GPIO controllers. - Support suspend/resume in the Tegra driver. - Support pull-up on the Broadcom BCM2711. - The Intel driver can now request locked pads. - Fix the UFS reset pin in the Qualcomm SDM845 driver" * tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux() pinctrl: bcm: remove redundant assignment to pointer log pinctrl: iproc: Add 'get_direction' support pinctrl: iproc-gpio: Handle interrupts for multiple instances pinctrl: iproc-gpio: Fix incorrect pinconf configurations pinctrl: intel: mark intel_pin_to_gpio __maybe_unused pinctrl: qcom: sdm845: Fix UFS_RESET pin pinctrl: mvebu: add additional variant for standalone CP115 pinctrl: mvebu: Add CP110 missing pin functionality dt-bindings: cp110: document the new CP115 pinctrl compatible pinctrl: bcm2835: Pass irqchip when adding gpiochip pinctrl: meson: meson: Add of_node_put() before return pinctrl/gpio: Take MUX usage into account dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support pinctrl: amd: disable spurious-firing GPIO IRQs pinctrl: rza2: Include the appropriate headers pinctrl: rza2: Drop driver use of consumer flags ...
| * Merge tag 'v5.3-rc5' into develLinus Walleij2019-08-215-38/+75
| |\ | | | | | | | | | Linux 5.3-rc5
| * | pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ↵Nathan Chancellor2019-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ctx parameter clang errors: drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' with an expression of type 'int (const struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' [-Werror,-Wincompatible-pointer-types] .set = aspeed_g6_sig_expr_set, ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") changed the set function pointer declaration and the g6 one wasn't updated (I assume because it wasn't merged yet). Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Link: https://github.com/ClangBuiltLinux/linux/issues/632 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20190807003037.48457-1-natechancellor@gmail.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Document existence of deprecated compatiblesAndrew Jeffery2019-08-052-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise they look odd in the face of not being listed in the bindings documents. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724081313.12934-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Add AST2600 pinmux supportAndrew Jeffery2019-08-053-0/+2404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Add SIG_DESC_CLEAR() helperAndrew Jeffery2019-08-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The complement of SIG_DESC_SET(). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Add multiple pin group support for functionsAndrew Jeffery2019-08-053-1489/+1789
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Add PIN_DECL_3() helperAndrew Jeffery2019-08-051-32/+40
| | | | | | | | | | | | | | | | | | | | | | | | This case is common in the AST2600, so add to the collection. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Rename pin declaration macrosAndrew Jeffery2019-08-053-405/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: aspeed: Fix spurious mux failures on the AST2500Andrew Jeffery2019-09-123-6/+38
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang <wangzqbj@inspur.com> Tested-by: John Wang <wangzqbj@inspur.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Make aspeed_pinmux_ips staticYueHaibing2019-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix sparse warning: drivers/pinctrl/aspeed/pinmux-aspeed.c:8:12: warning: symbol 'aspeed_pinmux_ips' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190711142457.37028-1-yuehaibing@huawei.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed-g5: Delay acquisition of regmapsAndrew Jeffery2019-07-294-37/+74
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.3-1' of ↵Linus Torvalds2019-07-147-753/+1089
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
| * pinctrl: aspeed: Strip moved macros and structs from private headerAndrew Jeffery2019-07-101-498/+0
| | | | | | | | | | | | | | | | | | | | | | | | Further cleanup from the SPDX fixup fallout for the recent ASPEED series. aspeed_g4_defconfig, aspeed_g5_defconfig and multi_v5_defconfig now compile. Smoke tested the g4 and g5 kernels under QEMU's palmetto-bmc and romulus-bmc machines respectively. Fixes: 35d8510ea3ad ("pinctrl: aspeed: Fix missed include") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190710032216.4088-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Fix missed includeLinus Walleij2019-07-101-0/+2
| | | | | | | | | | | | | | | | | | Some SPDX churn made my fixes drop an important include from the Aspeed pinctrl header. Fix it up. Cc: Andrew Jeffery <andrew@aj.id.au> Reported-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Add implementation-related documentationAndrew Jeffery2019-07-031-4/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ASPEED pinctrl driver implementations make heavy use of macros to minimise tedium of implementation and maximise the chance that the compiler will catch errors in defining signal and pin configurations. While the goal of minimising errors is achieved, it is at the cost of the complexity of the macros. Document examples of the expanded form of pin declarations to demonstrate the operation of the macros. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Split out pinmux from general pinctrlAndrew Jeffery2019-07-037-255/+888
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Clarify comment about strapping W1CAndrew Jeffery2019-07-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping register. The information was correct if you squinted while reading, but hopefully switching the order of the registers as listed conveys it better. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Correct comment that is no longer trueAndrew Jeffery2019-07-031-2/+1
| | | | | | | | | | | | | | | | | | | | We have handled the GFX register case for quite some time now. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Add SGPM pinmuxHongwei Zhang2019-06-081-0/+4
| | | | | | | | | | | | | | | | | | Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-304-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
|/ | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* pinctrl: aspeed: Wrap -Woverride-init with cc-optionNathan Chancellor2018-12-161-1/+1
| | | | | | | | | | | | | Clang does not support this option: warning: unknown warning option '-Woverride-init'; did you mean '-Woverride-module'? [-Wunknown-warning-option] 1 warning generated. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: remove unnecessary unlikely()Igor Stoppa2018-08-311-1/+1
| | | | | | | | | | WARN_ON() already contains an unlikely(), so it's not necessary to wrap it into another. Signed-off-by: Igor Stoppa <igor.stoppa@huawei.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Fix documentationJoel Stanley2018-06-281-2/+2
| | | | | | | | | | | | | Fixes these warnings: pinctrl-aspeed.c:112: warning: Function parameter or member 'map' not described in 'aspeed_sig_desc_eval' pinctrl-aspeed.c:112: warning: Excess function parameter 'regmap' description in 'aspeed_sig_desc_eval' Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Rework strap register write logic for the AST2500Andrew Jeffery2017-08-311-10/+16
| | | | | | | | | | | | | | | | | | Yong Li found that writes to the AST2500 strapping register were not properly supported by the Aspeed pinctrl core and provided a patch to rectify the problem. Several revisions of the patch were posted and ultimately v4 should have been applied, however some unfortunate liberal application of tags on my part lead to confusion between v3[1] and v4[2]. Generate the diff between v3 and v4 to apply as a fixup patch. [1] http://patchwork.ozlabs.org/patch/801662/ [2] http://patchwork.ozlabs.org/patch/802946/ Cc: Yong Li <sdliyong@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Fix ast2500 strap register write logicYong Li2017-08-222-2/+18
| | | | | | | | | | On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by: Yong Li <sdliyong@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall2017-08-221-3/+3
| | | | | | | | | | | | | structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g4: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall2017-08-221-2/+2
| | | | | | | | | | | | | structures These structures are only stored in fields of a pinctrl_desc structure (pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g5: Add USB device and host supportAndrew Jeffery2017-08-141-1/+57
| | | | | | | | | | Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g4: Add USB device and host supportAndrew Jeffery2017-08-141-7/+59
| | | | | | | | | | | | | | | | Implement the AST2400 USB functions as described by the devicetree bindings. Three ports are fully documented in the datasheet and exposed through the bindings and pinctrl, though there are remnants of documentation for a fourth port muxed with GPIO pins GPIOQ6 and GPIOQ7. The implementation is updated to reflect this but the function and group are not exposed. Disregarding the mostly undocumented fourth port, the USB functions are an outlier with respect to the rest of the muxed functionality on the AST2400 as GPIO is not supported on these pins. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g5: Add pinconf supportAndrew Jeffery2017-04-241-1/+152
| | | | | | | | | Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: g4: Add pinconf supportAndrew Jeffery2017-04-241-1/+116
| | | | | | | | | Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Add core pinconf supportAndrew Jeffery2017-04-242-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several pinconf parameters have a fairly straight-forward mapping onto the Aspeed pin controller. These include management of pull-down bias, drive-strength, and some debounce configuration. Pin biasing largely is managed on a per-GPIO-bank basis, aside from the ADC and RMII/RGMII pins. As the bias configuration for each pin in a bank maps onto a single per-bank bit, configuration tables will be introduced to describe the ranges of pins and the supported pinconf parameter. The use of tables also helps with the sparse support of pinconf properties, and the fact that not all GPIO banks support biasing or drive-strength configuration. Further, as the pin controller uses a consistent approach for bias and drive strength configuration at the register level, a second table is defined for looking up the the bit-state required to enable or query the provided configuration. Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU. The test method was to set the appropriate bits via devmem and verify the result through the controller's pinconf-pins debugfs file. This simultaneously validates the get() path and half of the set() path. The remainder of the set() path was validated by configuring a handful of pins via the devicetree with the supported pinconf properties and verifying the appropriate registers were touched. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Fix unused-const-variable warningsAndrew Jeffery2017-04-111-6/+6
| | | | | | | | Three video input signals suffered from a search/replace failure in some copied code. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Allow disabling Port D and Port E loopback modeRick Altherr2017-03-141-2/+12
| | | | | | | | | | | | | | | | | | | | | Port D and port E GPIO loopback modes are commonly enabled via hardware straps for use with front-panel buttons. When the BMC is powered off or fails to boot, the front-panel buttons are directly connected to the host chipset via the loopback to allow direct power-on and reset control. Once the BMC has booted, the loopback mode must be disabled for the BMC to take over control of host power-on and reset. Disabling these loopback modes requires writing to the hardware strap register which violates the current design of assuming the system designer chose the strap settings for a specific reason and they should be treated as read-only. Only the two bits of the strap register related to these loopback modes are allowed to be written and comments have been added to explain why. Signed-off-by: Rick Altherr <raltherr@google.com> Acked-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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