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* pinctrl: intel: Add Intel Meteor Point pin controller and GPIO supportAndy Shevchenko2023-12-151-0/+9
| | | | | | | | | This driver supports pinctrl/GPIO hardware found on Intel Meteor Point (a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces including GPIO interrupts. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Add a generic Intel pin control platform driverAndy Shevchenko2023-11-141-0/+10
| | | | | | | | | | | New generations of Intel platforms will provide better description of the pin control devices in the ACPI tables. Hence, we may provide a generic pin control platform driver to cover all of them. Currently the following Intel SoCs / platforms require this to be functional: - Lunar Lake Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: allow independent COMPILE_TESTRaag Jadav2023-11-131-1/+1
| | | | | | | | | Now that we have completed the transition to standard ACPI helpers for the entire Intel pinctrl tree, we can detach COMPILE_TEST from ACPI dependency. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: consolidate ACPI dependencyRaag Jadav2023-08-221-19/+1
| | | | | | | | | Since all the Intel specific platform drivers depend on ACPI, we can consolidate their config dependency. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Merge patch series "Reuse common functions from pinctrl-intel"Andy Shevchenko2023-08-151-5/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raag Jadav <raag.jadav@intel.com> says: This series exports common pinctrl functions that are used across Intel specific platform drivers to PINCTRL_INTEL namespace and reuses them into Baytrail, Cherryview and Lynxpoint drivers. This helps reduce their code and memory footprint. X86 kernels are fairly unikernels such that pinctrl-intel driver is enabled by most Linux distributions and most Intel specific platform drivers (inside drivers/pinctrl/intel) depend on it. The only exception to this is Lynxpoint. But taking into account its fairly old age, it wouldn't suffer much from pinctrl-intel dependency. bloat-o-meter: ============== Intel: add/remove: 17/10 grow/shrink: 0/0 up/down: 375/-319 (56) Total: Before=9598, After=9654, chg +0.58% Baytrail: add/remove: 1/6 grow/shrink: 0/2 up/down: 41/-441 (-400) Total: Before=16538, After=16138, chg -2.42% Cherryview: add/remove: 1/6 grow/shrink: 2/0 up/down: 90/-272 (-182) Total: Before=18133, After=17951, chg -1.00% Lynxpoint: add/remove: 1/6 grow/shrink: 0/1 up/down: 24/-354 (-330) Total: Before=7836, After=7506, chg -4.21% Link: https://lore.kernel.org/r/20230814060311.15945-1-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * pinctrl: lynxpoint: reuse common functions from pinctrl-intelRaag Jadav2023-08-151-5/+1
| | | | | | | | | | | | | | | | | | | | Reuse common functions from pinctrl-intel driver. While at it, select pinctrl-intel for Intel Lynxpoint driver. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-5-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | pinctrl: moorefield: Adapt to Intel Tangier driverRaag Jadav2023-08-151-11/+0
| | | | | | | | | | | | | | | | Make use of Intel Tangier as a library driver for Moorefield. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | pinctrl: merrifield: Adapt to Intel Tangier driverRaag Jadav2023-08-151-11/+0
| | | | | | | | | | | | | | | | Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | pinctrl: tangier: Introduce Intel Tangier driverRaag Jadav2023-08-151-0/+1
|/ | | | | | | | | Intel Tangier implements the common pinctrl functionalities for Merrifield and Moorefield platforms. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Add Intel Moorefield pin controller supportAndy Shevchenko2022-11-081-0/+11
| | | | | | | | | | | This driver adds pinctrl support for Intel Moorefield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver, which supports this pinctrl interface, will be submitted separately. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Add Intel Meteor Lake pin controller supportAndy Shevchenko2022-06-301-0/+8
| | | | | | | | | This driver adds pinctrl/GPIO support for Intel Meteor Lake. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Kconfig: Add configuration menu to Intel pin controlCai Huoqing2021-10-261-3/+3
| | | | | | | | | | Adding a configuration menu to hold many Intel pin control drivers helps to make the display more concise. Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Alder Lake-S pin controller supportAndy Shevchenko2020-11-041-0/+8
| | | | | | | | | This driver adds pinctrl/GPIO support for Intel Alder Lake-S SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add Intel Elkhart Lake pin controller supportAndy Shevchenko2020-11-041-0/+8
| | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Elkhart Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add blank line before endif in KconfigAndy Shevchenko2020-11-021-0/+1
| | | | | | | Add a blank line before endif directive in Kconfig for better readability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add Intel Lakefield pin controller supportAndy Shevchenko2020-11-021-0/+8
| | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Lakefield SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: cherryview: Switch to use intel_pinctrl_get_soc_data()Andy Shevchenko2020-08-201-5/+1
| | | | | | | | Since we have common helper to retrieve SoC data from driver data we may switch to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: baytrail: Switch to use intel_pinctrl_get_soc_data()Andy Shevchenko2020-08-201-5/+1
| | | | | | | | Since we have common helper to retrieve SoC data from driver data we may switch to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add Intel Emmitsburg pin controller supportAndy Shevchenko2020-07-211-0/+8
| | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add Intel Jasper Lake pin controller supportAndy Shevchenko2020-04-141-0/+8
| | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: lynxpoint: Switch to pin control APIAndy Shevchenko2019-12-131-0/+3
| | | | | | | | When all preparations are done, we may switch to pin control API. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: lynxpoint: Move GPIO driver to pin controller folderAndy Shevchenko2019-12-131-0/+10
| | | | | | | | | Move Lynxpoint GPIO driver under Intel pin control umbrella for further transformation to a real pin control driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add Intel Tiger Lake pin controller supportAndy Shevchenko2019-10-301-0/+7
| | | | | | | | | This driver adds pinctrl/GPIO support for Intel Tiger Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: intel: Convert to use SPDX identifierAndy Shevchenko2018-07-021-2/+2
| | | | | | | | | | Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Ice Lake PCH pin controller supportAndy Shevchenko2018-06-291-0/+8
| | | | | | | | | | This adds pinctrl/GPIO support for Intel Ice Lake PCH. The Ice Lake PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Cedar Fork PCH pin controller supportMika Westerberg2017-10-311-0/+8
| | | | | | | | | Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO driver to support it. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Do not depend in GPIOLIB, select itLinus Walleij2017-10-121-1/+2
| | | | | | | | | | | | | | | | | Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Lewisburg GPIO supportMika Westerberg2017-08-221-0/+8
| | | | | | | | | Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H except few differences in register offsets and pin lists. Because of this we add a separate pinctrl driver for Lewisburg. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Denverton pin controller supportMika Westerberg2017-08-141-0/+8
| | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Denverton SoC. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: wrap Intel pin control drivers in an architecture checkPeter Robinson2017-08-141-0/+3
| | | | | | | | | | The Intel pin control drivers are architecture specific so add an if arch to check for X86 or compile test to ensure continued test coverage. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Cannon Lake PCH pin controller supportMika Westerberg2017-06-091-0/+8
| | | | | | | | | This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Gemini Lake pin controller supportMika Westerberg2017-01-301-0/+8
| | | | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Gemini Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. This commit includes material from David E. Box. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Merrifield pin controller supportAndy Shevchenko2016-06-291-0/+11
| | | | | | | | | | This driver adds pinctrl support for Intel Merrifield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver (gpio-intel-mid.c) will be updated accordingly to support pinctrl interface. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: Add pin control operationsCristina Ciocan2016-04-041-0/+3
| | | | | | | | | | | | | | | | | | Add implementation for: - pin control, group information retrieval: count, name and pins - pin muxing: - function information (count, name and groups) - mux setting - gpio control (enable, disable, set direction) - pin configuration: - pull disable - pull up/down and pull strength - debounce - any other option is treated as not supported. Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Broxton pin controller supportMika Westerberg2015-10-271-0/+8
| | | | | | | | | This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO supportMika Westerberg2015-04-071-0/+17
| | | | | | | | | | | | | | This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO interrupts). The driver is split into core and platform parts so that the same core driver can be reused in other drivers for other Intel GPIO hardware that is based on the same host controller design. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add Intel Cherryview/Braswell pin controller supportMika Westerberg2014-11-041-0/+12
| | | | | | | | | | | | This driver supports the pin/GPIO controllers found in newer Intel SoCs like Cherryview and Braswell. The driver provides full GPIO support and minimal set of pin controlling funtionality. The driver is based on the original Cherryview GPIO driver authored by Ning Li and Alan Cox. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Move Intel Baytrail pinctrl driver under intel directoryMika Westerberg2014-10-291-0/+15
We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-26 19:45:54 +0100