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* pinctrl: intel: Add Intel Moorefield pin controller supportAndy Shevchenko2022-11-083-0/+928
| | | | | | | | | | | This driver adds pinctrl support for Intel Moorefield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver, which supports this pinctrl interface, will be submitted separately. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: merrifield: Use temporary variable for struct deviceAndy Shevchenko2022-11-031-8/+7
| | | | | | | Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Use temporary variable for struct deviceAndy Shevchenko2022-11-031-11/+12
| | | | | | | Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Use str_enable_disable() helperAndy Shevchenko2022-10-261-1/+2
| | | | | | | Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tigerlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-14/+14
| | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: sunrisepoint: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-16/+16
| | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: icelake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-4/+4
| | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: cannonlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-4/+4
| | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: alderlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-24/+16
| | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Add missing header(s)Andy Shevchenko2022-10-241-2/+4
| | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: merrifield: Add missing header(s)Andy Shevchenko2022-10-241-1/+3
| | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: lynxpoint: Add missing header(s)Andy Shevchenko2022-10-241-2/+4
| | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: cherryview: Add missing header(s)Andy Shevchenko2022-10-241-2/+4
| | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* Merge tag 'pinctrl-v6.0-1' of ↵Linus Torvalds2022-08-109-53/+470
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ...
| * pinctrl: intel: Add Intel Meteor Lake pin controller supportAndy Shevchenko2022-06-303-0/+426
| | | | | | | | | | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Meteor Lake. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: intel: Drop no more used members of struct intel_pingroupAndy Shevchenko2022-06-201-9/+0
| | | | | | | | | | | | | | There are no more used members in the struct intel_pingroup, drop them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: intel: Switch to to embedded struct pingroupAndy Shevchenko2022-06-201-7/+7
| | | | | | | | | | | | | | Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: merrifield: Switch to to embedded struct pingroupAndy Shevchenko2022-06-201-7/+7
| | | | | | | | | | | | | | Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: lynxpoint: Switch to to embedded struct pingroupAndy Shevchenko2022-06-201-5/+5
| | | | | | | | | | | | | | Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: cherryview: Switch to to embedded struct pingroupAndy Shevchenko2022-06-201-8/+8
| | | | | | | | | | | | | | Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: baytrail: Switch to to embedded struct pingroupAndy Shevchenko2022-06-201-9/+9
| | | | | | | | | | | | | | Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: intel: Embed struct pingroup into struct intel_pingroupAndy Shevchenko2022-06-201-8/+8
| | | | | | | | | | | | | | | | | | Add a new member to the struct intel_pingroup to cover generic pin control group parameters. The idea is to convert all users (one-by-one) to it and drop old members later on. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* | pinctrl: intel: Check against matching data instead of ACPI companionAndy Shevchenko2022-07-141-8/+6
|/ | | | | | | | | | | | | | | | | | In some cases we may get a platform device that has ACPI companion which is different to the pin control described in the ACPI tables. This is primarily happens when device is instantiated by board file. In order to allow this device being enumerated, refactor intel_pinctrl_get_soc_data() to check the matching data instead of ACPI companion. Reported-by: Henning Schild <henning.schild@siemens.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
* pinctrl: intel: Fix kernel doc format, i.e. add return sectionsAndy Shevchenko2022-05-201-0/+5
| | | | | | | | | | | | | | Kernel doc validator is not happy: pinctrl-intel.c:865: warning: No description found for return value of 'intel_gpio_to_pin' pinctrl-intel.c:904: warning: No description found for return value of 'intel_pin_to_gpio' 2 warnings Add return sections to the kernel documentation of the above mentioned functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Drop unused irqchip member in struct intel_pinctrlAndy Shevchenko2022-05-181-2/+0
| | | | | | | There is no users of irqchip member in struct intel_pinctrl. Drop it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: make irq_chip immutableAndy Shevchenko2022-05-181-15/+25
| | | | | | | | | | | | Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()Andy Shevchenko2022-05-171-4/+3
| | | | | | | | | The callers already have dereferenced pointer to GPIO chip, no need to do it again in chv_gpio_irq_mask_unmask(). Hence, replace IRQ data pointer by GPIO chip pointer. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: lynxpoint: make irq_chip immutableAndy Shevchenko2022-05-161-10/+16
| | | | | | | | | | | | | | | Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch hwirq variable to use the correct type for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: cherryview: make irq_chip immutableAndy Shevchenko2022-05-161-27/+38
| | | | | | | | | | | | | | | Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of pin for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: baytrail: make irq_chip immutableAndy Shevchenko2022-05-161-17/+25
| | | | | | | | | | | | | | | Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of offset for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: broxton: Add module alias for Intel Apollo LakeAndy Shevchenko2022-05-111-0/+1
| | | | | | | | | We have platform device IDs for Broxton and Apollo Lake, but module alias is provided only for the former. Make it consistent by providing an alias for Apollo Lake. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: alderlake: Fix register offsets for ADL-N variantAndy Shevchenko2022-04-061-20/+40
| | | | | | | | | | It appears that almost traditionally the N variants have deviations in the register offsets in comparison to S one. This is the case for Intel Alder Lake as well. Fix register offsets for ADL-N variant. Fixes: 114b610b9048 ("pinctrl: alderlake: Add Intel Alder Lake-N pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* Merge tag 'pinctrl-v5.18-1' of ↵Linus Torvalds2022-03-283-11/+652
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time. Just new driver code and improvements! New drivers: - New driver for the Broadcom BCM4908 SoC. - New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative of the Samsung Exynos pin control driver. - New driver for the Amlogic Meson S4 SoC. - New driver for the Sunplus SP7021 SoC. - New driver for the Microsemi Ocelot family ServalT SoC. - New subdriver for Intel Alder Lake-M SoC. - New subdriver for Intel Ice Lake-N SoC, including PCH support. - New subdriver for Renesas R8A779F0 SoC. - New subdriver for Mediatek MT8186 SoC. - New subdriver for NXP Freescale i.MX93 SoC. - New driver for Nuvoton WPCM450 SoC. - New driver for Qualcomm SC8280XP SoC. Improvements: - Wakeup support on Samsung Exynos850 and ExynosAutov9. - Serious and voluminous maintenance cleanup and refactoring in the Renesas drivers. Mainly sharing similar data between the different SoC subdrivers. - Qualcomm SM8450 EGPIO support. - Drive strength support on the Mediatek MT8195. - Add some missing groups and functions to the Ralink RT2880" * tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits) pinctrl: mediatek: common-v1: fix semicolon.cocci warnings pinctrl: nuvoton: wpcm450: Fix build error without OF pinctrl: qcom-pmic-gpio: Add support for pm8450 dt-bindings: pinctrl: aspeed: Update gfx node in example dt-bindings: pinctrl: rt2880: add missing pin groups and functions pinctrl: ingenic: Fix regmap on X series SoCs pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register() pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register() pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS pinctrl: nuvoton: Fix sparse warning pinctrl: mediatek: mt8186: Account for probe refactoring pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback pinctrl: mediatek: common-v1: Commonize spec_pupd callback pinctrl: mediatek: common-v1: Use common probe function pinctrl: mediatek: common-v1: Add common probe function pinctrl: mediatek: paris: Unify probe function by using OF match data pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe pinctrl: berlin: fix error return code of berlin_pinctrl_build_state() pinctrl: qcom: Introduce sc8280xp TLMM driver ...
| * pinctrl: icelake: Add Ice Lake-N PCH pin controller supportAndy Shevchenko2022-02-231-8/+283
| | | | | | | | | | | | | | | | | | This adds pinctrl/GPIO support for Intel Ice Lake-N PCH. The Ice Lake-N PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: alderlake: Add Intel Alder Lake-N pin controller supportAndy Shevchenko2022-02-231-1/+315
| | | | | | | | | | | | | | | | | | This change driver adds pinctrl/GPIO support for Intel Alder Lake-N SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: alderlake: Add Raptor Lake-S ACPI IDAndy Shevchenko2022-02-231-0/+1
| | | | | | | | | | | | | | | | | | Intel Raptor Lake-S PCH has the same GPIO hardware than Alder Lake-S PCH but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: tigerlake: Revert "Add Alder Lake-M ACPI ID"Andy Shevchenko2022-02-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | It appears that last minute change moved ACPI ID of Alder Lake-M to the INTC1055, which is already in the driver. This ID on the other hand will be used elsewhere. This reverts commit 258435a1c8187f559549e515d2f77fa0b57bcd27. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: baytrail: Clear direct_irq_en flag on broken configsHans de Goede2022-01-241-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards set the direct_irq_en flag in the conf0 register without setting the correct trigger bits. The direct_irq_en flag just means that the GPIO will send IRQs directly to the APIC instead of going through the shared interrupt for the GPIO controller, in order for the pin to be able to actually generate IRQs the trigger flags must configure the IRQ as a level-high or level-low active IRQ. Note testing shows that using edge trigger add the conf0 register level does NOT work, instead edge triggering should be set at the IO-APIC level. I believe that the direct_irq_en flag connects the output of the GPIO's IRQ trigger block, which normally sets the status flag in the IRQ status reg at 0x800 to one of the IO-APIC pins according to the direct IRQ mux. This means that the TRIG_LVL bit *must* be set, so that the GPIO's input value is directly passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, selecting edge mode operation then on the first edge the selected IO-APIC pin goes high, but since no write-to-clear write will be done to the IRQ status reg at 0x800, the detected edge condition will never get cleared. This APIC pin stuck high condition can be observed with the pin configured as level-high active, in the form of an interrupt storm. Clearing the TRIG_MASK bits of conf0 stops the storm, reconfiguring them as edge again results in a storm again as soon as the edge is triggered once. Detect invalid trigger flags, log a FW_BUG warning when encountering this and clear the direct_irq_en flag so that a driver can actually use the pin as IRQ through gpiod_to_irq(). Specifically this allows the edt-ft5x06 touchscreen driver to use INT33FC:02 pin 3 as touchscreen IRQ on the Nextbook Ares 8 tablet, accompanied by the following new log message byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger, clearing The new byt_direct_irq_sanity_check() function also checks that the pin is actually appointed to one of the 16 direct-IRQs which the GPIO controller supports and on success prints debug messages like these: byt_gpio INT33FC:02: Pin 0: uses direct IRQ 0 (IO-APIC 67) byt_gpio INT33FC:02: Pin 15: uses direct IRQ 2 (IO-APIC 69) This is useful to figure out the GPIO pin belonging to ACPI resources like this one: "Interrupt () { 0x00000043 }" or the other way around. The strict checking of valid trigger flags this introduces does result in FW_BUG messages on quite a few devices. E.g. on the Yoga Tablet 2 1051L: byt_gpio INT33FC:00: [Firmware Bug]: pin 92: direct_irq_en set but no IRQ assigned, clearing byt_gpio INT33FC:00: [Firmware Bug]: pin 93: direct_irq_en set but no IRQ assigned, clearing These 2 also have mux set to 7 and fall + rise + level trigger bits set, presumably something has written 0xffffffff to their conf0 registers byt_gpio INT33FC:02: Pin 3: uses direct IRQ 1 (IO-APIC 68) byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger (conf0: 2803cc00h), clearing Most tablets seem to have this, looking at DSDTs this seems intended for use with an I2C HID sensor-hub and is still set on devices without one. To make sure this does not cause any regressions this has been tested, including checking disabled direct-IRQs are not used in the DSDT, on the following devices: Asus ME176C Asus TF103C Chuwi Vi10 (with its Windows BIOS) HP x2 10-n000nd Lenovo Yoga Tablet 2 1050L (Android version, without EC, with buggy DSDT) Lenovo Yoga Tablet 2 1051L (Windows version, with EC) Suggested-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | Merge tag 'platform-drivers-x86-v5.18-1' of ↵Linus Torvalds2022-03-251-0/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 Pull x86 platform driver updates from Hans de Goede: "New drivers: - AMD Host System Management Port (HSMP) - Intel Software Defined Silicon Removed drivers (functionality folded into other drivers): - intel_cht_int33fe_microb - surface3_button amd-pmc: - s2idle bug-fixes - Support for AMD Spill to DRAM STB feature hp-wmi: - Fix SW_TABLET_MODE detection method (and other fixes) - Support omen thermal profile policy v1 serial-multi-instantiate: - Add SPI device support - Add support for CS35L41 amplifiers used in new laptops think-lmi: - syfs-class-firmware-attributes Certificate authentication support thinkpad_acpi: - Fixes + quirks - Add platform_profile support on AMD based ThinkPads x86-android-tablets: - Improve Asus ME176C / TF103C support - Support Nextbook Ares 8, Lenovo Tab 2 830 and 1050 tablets Lots of various other small fixes and hardware-id additions" * tag 'platform-drivers-x86-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (60 commits) platform/x86: think-lmi: Certificate authentication support Documentation: syfs-class-firmware-attributes: Lenovo Certificate support platform/x86: amd-pmc: Only report STB errors when STB enabled platform/x86: amd-pmc: Drop CPU QoS workaround platform/x86: amd-pmc: Output error codes in messages platform/x86: amd-pmc: Move to later in the suspend process ACPI / x86: Add support for LPS0 callback handler platform/x86: thinkpad_acpi: consistently check fan_get_status return. platform/x86: hp-wmi: support omen thermal profile policy v1 platform/x86: hp-wmi: Changing bios_args.data to be dynamically allocated platform/x86: hp-wmi: Fix 0x05 error code reported by several WMI calls platform/x86: hp-wmi: Fix SW_TABLET_MODE detection method platform/x86: hp-wmi: Fix hp_wmi_read_int() reporting error (0x05) platform/x86: amd-pmc: Validate entry into the deepest state on resume platform/x86: thinkpad_acpi: Don't use test_bit on an integer platform/x86: thinkpad_acpi: Fix compiler warning about uninitialized err variable platform/x86: thinkpad_acpi: clean up dytc profile convert platform/x86: x86-android-tablets: Depend on EFI and SPI platform/x86: amd-pmc: uninitialized variable in amd_pmc_s2d_init() platform/x86: intel-uncore-freq: fix uncore_freq_common_init() error codes ...
| * | pinctrl: baytrail: Add pinconf group + function for the pmu_clkHans de Goede2022-02-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the Lenovo Yoga Tablet 2 830 / 1050 / 1051 models the 32KHz PMU clk, which can be muxed externally to SUS pin 5 and/or 6 is used as a clock for the audio codec. On the 830 and 1050 models, with ship with Android as factory OS the pin-muxing for this is not setup by the BIOS. Add a pinconf group + function for the pmu_clk on SUS pin 5 and 6 to allow setting the pinmux up from within the x86-android-tablets platform code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220223133153.730337-2-hdegoede@redhat.com
* | | Merge tag 'intel-pinctrl-v5.17-5' of ↵Linus Walleij2022-02-191-1/+0
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.17-5 * Revert misplaced ID The following is an automated git shortlog grouped by driver: tigerlake: - Revert "Add Alder Lake-M ACPI ID"
| * | | pinctrl: tigerlake: Revert "Add Alder Lake-M ACPI ID"Andy Shevchenko2022-02-151-1/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that last minute change moved ACPI ID of Alder Lake-M to the INTC1055, which is already in the driver. This ID on the other hand will be used elsewhere. This reverts commit 258435a1c8187f559549e515d2f77fa0b57bcd27. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | | Merge tag 'intel-pinctrl-v5.17-4' of ↵Linus Walleij2022-01-301-28/+36
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.17-4 * Couple of fixes on how Intel driver handles an interrupt * Revert pin renaming change in ZynqMQ as it appears to be part of the Device Tree bindings * Fix ordering of the files in the Makefile The following is an automated git shortlog grouped by driver: intel: - Fix a glitch when updating IRQ flags on a preconfigured line - fix unexpected interrupt Place correctly CONFIG_PINCTRL_ST in the Makefile: - Place correctly CONFIG_PINCTRL_ST in the Makefile zynqmp: - Revert "Unify pin naming"
| * | pinctrl: intel: Fix a glitch when updating IRQ flags on a preconfigured lineAndy Shevchenko2022-01-241-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") hadn't taken into account an update of the IRQ flags scenario. When updating the IRQ flags on the preconfigured line the ->irq_set_type() is called again. In such case the sequential Rx buffer configuration changes may trigger a falling or rising edge interrupt that may lead, on some platforms, to an undesired event. This may happen because each of intel_gpio_set_gpio_mode() and __intel_gpio_set_direction() updates the pad configuration with a different value of the GPIORXDIS bit. Notable, that the intel_gpio_set_gpio_mode() is called only for the pads that are configured as an input. Due to this fact, integrate the logic of __intel_gpio_set_direction() call into the intel_gpio_set_gpio_mode() so that the Rx buffer won't be disabled and immediately re-enabled. Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") Reported-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Grace Kao <grace.kao@intel.com>
| * | pinctrl: intel: fix unexpected interruptŁukasz Bartosik2022-01-241-20/+34
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ASUS Chromebook C223 with Celeron N3350 crashes sometimes during cold booot. Inspection of the kernel log showed that it gets into an inifite loop logging the following message: ->handle_irq(): 000000009cdb51e8, handle_bad_irq+0x0/0x251 ->irq_data.chip(): 000000005ec212a7, 0xffffa043009d8e7 ->action(): 00000 IRQ_NOPROBE set unexpected IRQ trap at vector 7c The issue happens during cold boot but only if cold boot happens at most several dozen seconds after Chromebook is powered off. For longer intervals between power off and power on (cold boot) the issue does not reproduce. The unexpected interrupt is sourced from INT3452 GPIO pin which is used for SD card detect. Investigation relevealed that when the interval between power off and power on (cold boot) is less than several dozen seconds then values of INT3452 GPIO interrupt enable and interrupt pending registers survive power off and power on sequence and interrupt for SD card detect pin is enabled and pending during probe of SD controller which causes the unexpected IRQ message. "Intel Pentium and Celeron Processor N- and J- Series" volume 3 doc mentions that GPIO interrupt enable and status registers default value is 0x0. The fix clears INT3452 GPIO interrupt enabled and interrupt pending registers in its probe function. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Signed-off-by: Łukasz Bartosik <lb@semihalf.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* / pinctrl: cherryview: Trigger hwirq0 for interrupt-lines without a mappingHans de Goede2022-01-241-2/+3
|/ | | | | | | | | | | | | | | | | | | Commit bdfbef2d29dc ("pinctrl: cherryview: Don't use selection 0 to mark an interrupt line as unused") made the code properly differentiate between unset vs (hwirq) 0 entries in the GPIO-controller interrupt-line to GPIO pinnumber/hwirq mapping. This is causing some boards to not boot. This commit restores the old behavior of triggering hwirq 0 when receiving an interrupt on an interrupt-line for which there is no mapping. Fixes: bdfbef2d29dc ("pinctrl: cherryview: Don't use selection 0 to mark an interrupt line as unused") Reported-and-tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220104164238.253142-1-hdegoede@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: cherryview: Use temporary variable for struct deviceAndy Shevchenko2021-11-261-28/+29
| | | | | | Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: cherryview: Do not allow the same interrupt line to be used by 2 pinsHans de Goede2021-11-261-8/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is impossible to use the same interrupt line for 2 pins, this will result in the interrupts only being delivered to the IRQ handler for the pin for which chv_gpio_irq_type() was called last. The pinctrl-cherryview.c code relies on the BIOS to correctly setup the interrupt line, but there is a BIOS bug on at least the Medion Akoya E1239T and the GPD win models where both INT33FF:02 pin 8, used by the powerbutton and INT33FF:02 pin 21 used as IRQ input for the accelerometer are mapped to interrupt line 0. This causes 2 problems: 1. The accelerometer IRQ does not work, since the power button is probed later taking over the intr_lines[0] slot. 2. Since the accelerometer IRQ is not marked as wakeup, interrupt line 0 gets masked on suspend, causing the power button to not work to wake the system from suspend. Likewise on the Lenovo Yogabook, which has a touchscreen as keyboard and the keyboard half of the tablet also has a Wacom digitizer, the BIOS by default assigns the same interrupt line to the GPIOs used for their interrupts. Fix these problems by adding a check for this and assigning a new interrupt line to the 2nd pin for which chv_gpio_irq_type() gets called. With this fix in place the following 2 messages show up in dmesg on the Medion Akoya E1239T and the GPD win: cherryview-pinctrl INT33FF:02: interrupt line 0 is used by both pin 21 and pin 8 cherryview-pinctrl INT33FF:02: changing the interrupt line for pin 8 to 15 And the following gets logged on the Lenovo Yogabook: cherryview-pinctrl INT33FF:01: interrupt-line 0 is used by both pin 49 and pin 56 cherryview-pinctrl INT33FF:01: changing the interrupt line for pin 56 to 7 Note commit 9747070c11d6 ("Input: axp20x-pek - always register interrupt handlers") was added as a work around for the power button not being able to wakeup the system. This relies on using the PMIC's connection to the power button but that only works on systems with the AXP288 PMIC. Once this fix has been merged that workaround can be removed. Cc: Yauhen Kharuzhy <jekhor@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: cherryview: Don't use selection 0 to mark an interrupt line as unusedHans de Goede2021-11-261-2/+16
| | | | | | | | | | | | | | The selection 0 is a perfectly valid, so stop using it to have the special meaning of interrupt line not used in the intr_lines. Instead introduce a special CHV_INVALID_HWIRQ value, derived from INVALID_HWIRQ. which is never a valid selection and use that to indicate unused interrupt lines. Cc: Yauhen Kharuzhy <jekhor@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: baytrail: Set IRQCHIP_SET_TYPE_MASKED flag on the irqchipHans de Goede2021-11-231-1/+1
| | | | | | | | | | | | | | | | | | | The byt_irq_type function ends with the IRQ masked, this means that calls to irq_set_irq_type() while the IRQ is enabled end up masking it, which is wrong. Add the IRQCHIP_SET_TYPE_MASKED flag to fix this. This will make the IRQ core call mask() + unmask() on the IRQ around a set_type() call when the IRQ is enabled at the type of the call. Note in practice irq_set_irq_type() getting called while the IRQ is enabled almost never happens. I hit this with a buggy DSDT where a wrongly active (_STA returns 0xf) I2C ACPI devices point to an IRQ already in use by an _AEI handler, leading to the irq_set_irq_type() call in acpi_dev_gpio_irq_get_by() getting called while the IRQ is enabled. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 17:44:10 +0100