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Add missing PWM_F pin muxing for GPIOA_11 and GPIOZ_12.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220112211642.2248901-2-gary.bisson@boundarydevices.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules.
The default is still built-in, this only adds the option of building
as modules.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:
+------+--------------------------------------+--------------------------+
| | | |
| SoC | EE domain | AO domain |
+------+--------------------------------------+--------------------------+
|m8 | parse regs: | parse regs: |
|m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)|
|gxl | fixup: | fixup: |
|gxbb | no | pull-enable = pull; |
|axg | | |
+------+--------------------------------------+--------------------------+
|g12a | parse regs: | parse regs: |
|sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds |
| | fixup: | fixup: |
| | no | pull = gpio; |
| | | pull-enable = gpio; |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs: |
|later | gpio/mux (without ao domain) |
|SoCs | fixup: |
| | pull = gpio; pull-enable = gpio; ds = gpio; |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add the missing pinmux for the pwm_a function on the GPIOE_2 pin.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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add drive-strength bank regiter and bit value for G12A SoC
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.
Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.
For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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