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* pinctrl: nand: meson-gxl: fix missing data pinsYixun Lan2018-05-161-2/+2
| | | | | | | | | | The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reported-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: nand: meson-gxbb: fix missing data pinsYixun Lan2018-05-161-2/+2
| | | | | | | | | | The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: cd1e3b01c7d3 ("pinctrl: amlogic: gxbb: add nand pins") Reported-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: axg: add tdm pinsJerome Brunet2018-05-021-0/+107
| | | | | | | | Add the information related to the tdm pins of the A113D SoC Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signalsMartin Blumenstingl2018-05-021-1/+12
| | | | | | | | | | | | | These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b). The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add support for the Meson8m2 SoCMartin Blumenstingl2018-05-021-1/+9
| | | | | | | | | | | | Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins, no other differences were found so far). Add the new compatible strings for Meson8m2 to the existing Meson8 driver so we don't have to duplicate the whole driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.17-1' of ↵Linus Torvalds2018-04-031-8/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk updates from Linus Walleij: "New drivers: - Qualcomm SDM845: this is their new flagship SoC platform which seems to be targeted at premium mobile handsets. - Renesas R-Car M3-N SoC. - Renesas R8A77980 SoC. - NXP (ex Freescale) i.MX 6SLL SoC. - Mediatek MT2712 SoC. - Allwinner H6 SoC. Improvements: - Uniphier adds a few new functions and pins. - Renesas refactorings and additional pin definitions. - Improved pin groups for Axis Artpec6. Cleanup: - Drop the TZ1090 drivers. This platform is no longer maintained and is being deleted. - Drop ST-Ericsson U8540/U9540 support as this was never productified. - Overall minor fixes and janitorial" * tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: uniphier: add UART hardware flow control pin-mux settings pinctrl: sunxi: add support for the Allwinner H6 main pin controller pinctrl: sunxi: change irq_bank_base to irq_bank_map pinctrl: sunxi: introduce IRQ bank conversion function pinctrl: sunxi: refactor irq related register function to have desc pinctrl: msm8998: Remove owner assignment from platform_driver pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings pinctrl/amd: poll InterruptEnable bits in enable_irq pinctrl: ocelot: fix gpio direction pinctrl: mtk: fix check warnings. pintcrl: mtk: support bias-disable of generic and special pins simultaneously pinctrl: add mt2712 pinctrl driver pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0 pinctrl: imx: Add pinctrl driver support for imx6sll dt-bindings: imx: update pinctrl doc for imx6sll pinctrl: intel: Implement intel_gpio_get_direction callback pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency pinctrl: mediatek: mtk-common: use true and false for boolean values pinctrl: sunxi: always look for apb block ...
| * pinctrl: meson: meson8b: fix requesting GPIOs greater than GPIOZ_3Martin Blumenstingl2018-03-021-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson8b is a cost reduced variant of the Meson8 SoC. It's package size is smaller than Meson8. Unfortunately there are a few key differences which cannot be seen without close inspection of the code and the public S805 datasheet: - the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and GPIOX_15 GPIOs - the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and GPIOY_16 GPIOs - the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24, GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29 - the GPIOZ bank is missing completely - there is a new GPIO bank called "DIF" This means that Meson8b only has 83 actual GPIO lines. Without any holes there would be 130 GPIO lines in total (120 are inherited from Meson8 plus 10 new from the DIF bank). GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly the number of actual GPIO lines on Meson8b and also the value of meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6 (which used ID 100 prior to this patch, "base of the GPIO controller was 382) as an example: $ echo 482 > /sys/class/gpio/export export_store: invalid GPIO 482 This removes all non-existing pins from to dt-bindings header file (include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get compile-time (instead of runtime) errors if Meson8b .dts uses a pin that only exists on Meson8. Additionally the pinctrl-meson8b driver has to be updated to handle this new GPIO numbering. By default a struct meson_bank only handles GPIO banks where the pins are numbered consecutively because it calculates the bit offsets based on the GPIO IDs. This is solved by taking the original BANK() definition and splitting it into consecutive subsets (X0..11 and X16..21). The bit offsets for each new bank includes the skipped GPIOs (the definition of the "X0..11" bank is identical to the old "X" bank apart from the "last IRQ" field, the definition of the new, split "X16..21" bank takes the original "X" bank and adds 16 - the start of the new split bank - to the "first IRQ", pullen bit, pull bit, dir bit, out bit and in bit). Commit 984cffdeaeb7ea ("pinctrl: Fix gpio/pin mapping for Meson8b") fixed the same issue by setting "ngpio" (of the gpio_chip) to 130. Unfortunately this broke in db80f0e158e621 ("pinctrl: meson: get rid of unneeded domain structures"). The solution from this patch was considered to be better than the previous attempt at fixing this because it provides compile-time error checking for the GPIOs that exist on Meson8 but don't exist on Meson8b. The following pins were tested on an Odroid-C1 using the sysfs GPIO interface checking that their value (high or low) could be read: - GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6, GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19, GPIOX_20, GPIOX_21 - GPIOY_3, GPIOY_7, GPIOY_8 (some of these had to be pulled up because they were low by default, others were high by default so these had to be pulled down) Reported-by: Linus Lüssing <linus.luessing@c0d3.blue> Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson-axg: adjust uart_ao_b pin group namingYixun Lan2018-02-121-2/+2
|/ | | | | | | | | Simply adjust the pin group to _x _y _z style, as to keep the consistency in DT with previous naming scheme. Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-axg: adjust spicc pin namingYixun Lan2017-12-131-43/+43
| | | | | | | | | | | | | | According to datasheet, we should use numbers for the pin naming instead of letters. The patch here try to fix this to keep the consistency. This patch should not bring any functional change. Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Suggested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoCXingyu Chen2017-11-303-0/+982
| | | | | | | | | | Add new pinctrl driver for Amlogic's Meson-AXG SoC. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoCXingyu Chen2017-11-305-0/+185
| | | | | | | | | | | | | The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: rework pinmux opsJerome Brunet2017-10-1610-109/+194
| | | | | | | | | | | | | | | | | | | This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: separate soc driversJerome Brunet2017-10-168-69/+138
| | | | | | | | | | | | | | | | | | When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: remove unused pin_baseJerome Brunet2017-10-111-1/+0
| | | | | | | | | | | | | While removing the need to have pin_base defined in meson pinctrl drivers, I forgot to remove the corresponding field from the pinctrl_data structure. Fixing this now. Fixes: 70e5ecb1b994 ("pinctrl: meson: get rid of pin_base") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gx: add TEST_N i2s pinmuxJerome Brunet2017-10-112-1/+10
| | | | | | | | Add TEST_N pinmux for channel 6 and 7 of the i2s output Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: add missing GPIOX_22 pinJerome Brunet2017-10-051-0/+1
| | | | | | | | | | | GPIOX_22 is declared as a gpio but the id is no present in the pin table. This hole trigger an error while reading the pingroup debugfs entry GPIOX_22 is no routed externally. For all we know, it could an internal pin of SoC Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gx: TEST_N belongs to the AO controllerJerome Brunet2017-10-052-8/+8
| | | | | | | | | | On meson-gx platforms, TEST_N has been incorrectly declared in the EE controller while it belongs to AO controller. Move the pin to the appropriate controller Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: get rid of pin_baseJerome Brunet2017-10-055-25/+13
| | | | | | | | | | pin_base was used with the manually set pin offset in meson pinctrl. This is no longer the case, pin_base is 0 on every meson pinctrl controllers and should go away. Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: remove offset from pinctrlJerome Brunet2017-10-056-1741/+1697
| | | | | | | | | | | | | | Offset on meson pinctrl and gpios is something that was carried from the vendor driver, where there is a weird link between the 2 controllers. Since these 2 controllers are independent, this offset adds an unnecessary complexity. This patch remove this manually set offset and rely on pinctrl to figure out the gpio base offset Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: fix incorrect usage of ENOSYSJerome Brunet2017-09-211-1/+1
| | | | | | | | ENOSYS is special and should only be used for incorrect syscall number. It is not the case here. let's use ENOTSUPP instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: add tsin_a pinsJerome Brunet2017-06-161-0/+36
| | | | | | | | | | | | | | Add Tsin A pins to bank DV and X. We don't have a driver for the tsin yet but since the tsin A pinmux is enabled by default at boot time, declaring this pinmux is required to properly operate on GPIOX. Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output as the tsin A seems to have priority. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: add interrupts to pinctrl dataJerome Brunet2017-06-095-46/+63
| | | | | | | | | | Add GPIO interrupt information to pinctrl data. Added to the original version from Jerome was data for Meson GXL. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: remove non-existing pin GPIOX_22Heiner Kallweit2017-06-091-1/+0
| | | | | | | | | | | | | | | | | | After commit 34e61801a3b9 "pinctrl: meson-gxbb: Add missing GPIODV_18 pin entry" I started to get the following warning: "meson-pinctrl c8834000.periphs:pinctrl@4b0: names 119 do not match number of GPIOs 120" It turned out that not the mentioned commit has a problem, it just revealed another problem which had existed before. There is no PIN GPIOX_22 on Meson GXBB. Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Add Ethernet PHY LEDS pinsNeil Armstrong2017-05-291-0/+10
| | | | | | | | | The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs enables the Link and Activity LEDs signals. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Add CEC pinsNeil Armstrong2017-05-291-0/+10
| | | | | | | | Add the AO and EE domain CEC pins for the Amlogic Meson GXL SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: Add CEC pinsNeil Armstrong2017-05-291-0/+10
| | | | | | | | Add the AO and EE domain CEC pins for the Amlogic Meson GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Fix typo in AO SPDIF pinsNeil Armstrong2017-05-291-2/+2
| | | | | | | | | The AO SPDIF pins were incorrectly defined with the EE pin offset. Fixes: b840d649f9ec ("pinctrl: meson: gxl: add spdif output pins") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Fix typo in AO I2S pinsNeil Armstrong2017-05-291-2/+2
| | | | | | | | | The AO I2S pins were incorrectly defined with the EE pin offset. Fixes: 2899adf0422 ("pinctrl: meson: gxl: add i2s output pins") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: Add missing GPIODV_18 pin entryNeil Armstrong2017-05-291-0/+1
| | | | | | | | | GPIODV_18 entry was missing in the original driver push. Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Add missing GPIODV_18 pin entryNeil Armstrong2017-05-291-0/+1
| | | | | | | | | GPIODV_18 entry was missing in the original driver push. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxbb: Add SPI pins for SPICC controllerNeil Armstrong2017-05-291-0/+14
| | | | | | | | The SPICC controller has dedicated SPI pins, this patchs add the pins definition in the GXBB pinctrl driver Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-gxl: Add SPI pins for the SPICC controllerNeil Armstrong2017-05-291-0/+14
| | | | | | | | The SPICC controller has dedicated SPI pins, this patchs add the pins definition in the GXL pinctrl driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add the AO HDMI CEC pinMartin Blumenstingl2017-05-221-0/+9
| | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add support for the AO remote output pinMartin Blumenstingl2017-05-221-1/+3
| | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add support for the I2S and SPDIF pinsMartin Blumenstingl2017-05-221-0/+52
| | | | | | | | This adds support for the I2S and SPDIF input and output pins, similar to what we have on GXBB and GXL. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: meson8: add the PWM pinsMartin Blumenstingl2017-05-221-0/+62
| | | | | | | | | | | | | This adds the missing pins for the PWM controllers found in Amlogic Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D, PWM_E and PWM_F controllers. There is an additional PWM function with the name PWM_VS in the vendor kernel sources which seems to be used for external video input. Thus it's not part of this change as the IP block behind the pwm-meson driver is not responsible for these pins. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.12-1' of ↵Linus Torvalds2017-05-034-34/+227
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.12 cycle. The extra week before the merge window actually resulted in some of the type of fixes that usually arrive after the merge window already starting to trickle in from eager developers using -next, I'm impressed. I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal with the onset of Samsung patches. It works great. Apart from that it is a boring round, just incremental updates and fixes all over the place, no serious core changes or anything exciting like that. The most pleasing to see is Julia Cartwrights work to audit the irqchip-providing drivers for realtime locking compliance. It's one of those "I should really get around to looking into that" things that have been on my TODO list since forever. Summary: Core changes: - add bi-directional and output-enable pin configurations to the generic bindings and generic pin controlling core. New drivers or subdrivers: - Armada 37xx SoC pin controller and GPIO support. - Axis ARTPEC-6 SoC pin controller support. - AllWinner A64 R_PIO controller support, and opening up the AllWinner sunxi driver for ARM64 use. - Rockchip RK3328 support. - Renesas R-Car H3 ES2.0 support. - STM32F469 support in the STM32 driver. - Aspeed G4 and G5 pin controller support. Improvements: - a whole slew of realtime improvements to drivers implementing irqchips: BCM, AMD, SiRF, sunxi, rockchip. - switch meson driver to get the GPIO ranges from the device tree. - input schmitt trigger support on the Rockchip driver. - enable the sunxi (AllWinner) driver to also be used on ARM64 silicon. - name the Qualcomm QDF2xxx GPIO lines. - support GMMR GPIO regions on the Intel Cherryview. This fixes a serialization problem on these platforms. - pad retention support for the Samsung Exynos 5433. - handle suspend-to-ram in the AT91-pio4 driver. - pin configuration support in the Aspeed driver. Cleanups: - the final name of Rockchip RK1108 was RV1108 so rename the driver and variables to stay consistent" * tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl: mediatek: Add missing pinctrl bindings for mt7623 pinctrl: artpec6: Fix return value check in artpec6_pmx_probe() pinctrl: artpec6: Remove .owner field for driver pinctrl: tegra: xusb: Silence sparse warnings ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller" pinctrl: make artpec6 explicitly non-modular pinctrl: aspeed: g5: Add pinconf support pinctrl: aspeed: g4: Add pinconf support pinctrl: aspeed: Add core pinconf support pinctrl: aspeed: Document pinconf in devicetree bindings pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Remove ngpios from stm32-pinctrl binding pinctrl: stm32: replace device_initcall() with arch_initcall() pinctrl: stm32: add possibility to use gpio-ranges to declare bank range pinctrl: armada-37xx: Add gpio support pinctrl: armada-37xx: Add pin controller support for Armada 37xx pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers pinctrl: core: Make pinctrl_init_controller() static pinctrl: generic: Add bi-directional and output-enable ...
| * pinctrl: meson: meson8b: rename the NAND DQS pin definitionsMartin Blumenstingl2017-04-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: meson8b: fix the NAND DQS pinsMartin Blumenstingl2017-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: gxl: add spdif output pinsJerome Brunet2017-03-281-0/+18
| | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: gxl: add i2s output pinsJerome Brunet2017-03-281-0/+31
| | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: gxbb: add spdif output pinsJerome Brunet2017-03-281-0/+18
| | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: gxbb: add i2s output pinsJerome Brunet2017-03-281-0/+31
| | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: use gpio-ranges from DTNeil Armstrong2017-03-281-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | When trying to add a gpio-hog, we enter a weird loop where the gpio-ranges is needed when gpiochip_add_data() is called but in the current implementation the ranges are added from the driver afterwards. A simple solution is to rely on the DR gpio-ranges attribute and remove the call to gpiochip_add_pin_range(). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson-gxl: Fix inverted registers and add missing pinsNeil Armstrong2017-03-281-15/+68
| | | | | | | | | | | | | | | | Fix some inverted bit numbers in some pinctrl groups and add missing pins and groups to be in pair with the GXBB pinctrl pins definition. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: gxl: add the missing PWM pin definitionsMartin Blumenstingl2017-03-231-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the missing PWM pins on Meson GXL SoCs, namely: - PWM_A - PWM_B - PWM_C - PWM_F (GPIOX_7 and GPIOCLK_1 can be selected as output) - PWM_AO_A (GPIOAO_3 and GPIOAO_8 can be selected as output) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson-gxbb: Fix typo in i2c ao groupsNeil Armstrong2017-03-231-2/+2
|/ | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v4.10-rc6' into develLinus Walleij2017-01-303-9/+7
|\ | | | | | | | | | | | | | | Linux 4.10-rc6 Resolved conflicts in: drivers/pinctrl/pinctrl-amd.c drivers/pinctrl/samsung/pinctrl-exynos.c
| * pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXMMartin Blumenstingl2017-01-192-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GXBB and GXL/GXM pinctrl drivers had a configuration which conflicts with uart_ao_a. According to the GXBB ("S905") datasheet the AO UART functions are: - GPIOAO_0: Func1 = UART_TX_AO_A (bit 12), Func2 = UART_TX_AO_B (bit 26) - GPIOAO_1: Func1 = UART_RX_AO_A (bit 11), Func2 = UART_RX_AO_B (bit 25) - GPIOAO_4: Func2 = UART_TX_AO_B (bit 24) - GPIOAO_5: Func2 = UART_RX_AO_B (bit 25) The existing definition for uart_AO_A already uses GPIOAO_0 and GPIOAO_1. The old definition of uart_AO_B however was broken, as it used GPIOAO_0 for TX (which would be fine) and two pins (GPIOAO_1 and GPIOAO_5) for RX (which does not make any sense). This fixes the uart_AO_B configuration by moving it to GPIOAO_4 and GPIOAO_5 (it would be possible to use GPIOAO_0 and GPIOAO_1 in theory, but all existing hardware uses uart_AO_A there). The fix for GXBB and GXL/GXM is identical since it seems that these specific pins are identical on both SoC variants. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: meson: fix gpio request disabling other modesNeil Armstrong2016-12-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl_gpio_request is called with the "full" gpio number, already containing the base, then meson_pmx_request_gpio is then called with the final pin number. Remove the base addition when calling meson_pmx_disable_other_groups. Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs") CC: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 20:45:52 +0100