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* pinctrl: rockchip: Only mask interrupts; never disableDoug Anderson2015-01-301-35/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip GPIO interrupt controller totally throws away all status about an interrupt when you "disable" the interrupt. That has unfortunate consequences in the following situation: 1. An edge-triggered interrupt is enabled and should wake the system. 2. System suspend happens: interrupt is disabled and marked for wake. 3. rockchip_irq_suspend() reenables the interrupt so we can wake. 4. Interrupt happens when asleep. 5. rockchip_irq_resume() redisables the interrupt. 6. Disabling the interrupt throws away all status about it. 7. Normal system resume happens and we enable the interrupt again, since we threw away status about the interrupt we don't know it fired while suspended. Even worse: if we need both edges of the interrupt the logic to swap edges never runs. Note: even if we somehow can post the status about wakeup interrupts in rockchip_irq_resume() we would still have a window of losing any edges that came in while interrupts were disabled. If we use mask only then we don't need to worry. The GPIO Interrupt controller keeps track of pending interrupts that are enabled and just masked. There was no real strong reason to support the enable/disable functionality (other than that it seemed right), so let's go back to just supporting mask/unmask but actually map it to the real mask/unmask. This ends up with slightly different (and more correct) behavior than before (f2dd028 pinctrl: rockchip: Fix enable/disable/mask/unmask). Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v3.19-rc6' into develLinus Walleij2015-01-301-28/+74
|\ | | | | | | Linux 3.19-rc6
| * pinctrl: rockchip: Avoid losing interrupts when supporting both edgesDoug Anderson2015-01-141-25/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was seeing cases where I was losing interrupts when inserting and removing SD cards. Sometimes the card would get "stuck" in the inserted state. I believe that the problem was related to the code to handle the case where we needed both rising and falling edges. This code would disable the interrupt as the polarity was switched. If an interrupt came at the wrong time it could be lost. We'll match what the gpio-dwapb.c driver does upstream and change the interrupt polarity without disabling things. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: Fix enable/disable/mask/unmaskDoug Anderson2014-12-301-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip pinctrl driver was only implementing the "mask" and "unmask" operations though the hardware actually has two distinct things: enable/disable and mask/unmask. It was implementing the "mask" operations as a hardware enable/disable and always leaving all interrupts unmasked. I believe that the old system had some downsides, specifically: - (Untested) if an interrupt went off while interrupts were "masked" it would be lost. Now it will be kept track of. - If someone wanted to change an interrupt back into a GPIO (is such a thing sensible?) by calling irq_disable() it wouldn't actually take effect. That's because Linux does some extra optimizations when there's no true "disable" function: it does a lazy mask. Let's actually implement enable/disable/mask/unmask properly. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: Handle wakeup pinsDoug Anderson2014-12-301-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rockchip pinctrl driver was using irq_gc_set_wake() as its implementation of irq_set_wake() but was totally ignoring everything that irq_gc_set_wake() did (which is to upkeep gc->wake_active). Let's fix that by setting gc->wake_active as GPIO_INTEN at suspend time and restoring GPIO_INTEN at resume time. NOTE a few quirks when thinking about this patch: - Rockchip pinctrl hardware supports both "disable/enable" and "mask/unmask". Right now we only use "disable/enable" and present those to Linux as "mask/unmask". This should be OK because enable/disable is optional and Linux will implement it in terms of mask/unmask. At the moment we always tell hardware all interrupts are unmasked (the boot default). - At suspend time Linux tries to call "disable" on all interrupts and also enables wakeup on all wakeup interrupts. One would think that since "disable" is implemented as "mask" when "disable" isn't provided and that since we were ignoring gc->wake_active that nothing would have woken us up. That's not the case since Linux "optimizes" things and just leaves interrutps unmasked, assuming it could mask them later when they go off. That meant that at suspend time all interrupts were actually being left enabled. With this patch random non-wakeup interrupts no longer wake the system up. Wakeup interrupts still wake the system up. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: pinconf-generic: Allow driver to specify DT paramsSoren Brinkmann2015-01-111-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally to the generic DT parameters, allow drivers to provide driver-specific DT parameters to be used with the generic parser infrastructure. To achieve this 'struct pinctrl_desc' is extended to pass custom pinconf option to the core. In order to pass this kind of information, the related data structures - 'struct pinconf_generic_dt_params', 'pin_config_item' - are moved from pinconf internals to the pinconf-generic header. Additionally pinconfg-generic is refactored to not only iterate over the generic pinconf parameters but also take the parameters into account that are provided through the driver's 'struct pinctrl_desc'. In particular 'pinconf_generic_parse_dt_config()' and 'pinconf_generic_dump' helpers are split into two parts each. In order to have a more generic helper that can be used to process the generic parameters as well as the driver-specific ones. v2: - fix typo - add missing documentation for @conf_items member in struct - rebase to pinctrl/devel: conflict in abx500 - rename _pinconf_generic_dump() to pinconf_generic_dump_one() - removed '_' from _parse_dt_cfg() - removed BUG_ONs, error condition is handled in if statements - removed pinconf_generic_dump_group() & pinconf_generic_dump_pin helpers - fixed up corresponding call sites - renamed pinconf_generic_dump() to pinconf_generic_dump_pins() - added kernel-doc to pinconf_generic_dump_pins() - add kernel-doc - more verbose commit message Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-151-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * pinctrl: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0
| | | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resumeChris Zhong2014-10-311-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288 would modify it to sdmmc0_det, so it need to be restored to the correct setting after resume from Maskrom. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl: rockchip: add suspend/resume functionsChris Zhong2014-10-311-0/+18
| | | | | | | | | | | | | | | | | | | | | | support suspend/resume of pinctrl, it allows handling sleep mode for hogged pins in pinctrl Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl: rockchip: Protect read-modify-write with the spinlockDoug Anderson2014-10-291-0/+18
| | | | | | | | | | | | | | | | There were a few instances where the rockchip pinctrl driver would do read-modify-write with no spinlock. Add a spinlock for these cases. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl: rockchip: Parse pin groups before calling pinctrl_register()Doug Anderson2014-10-291-6/+4
| | | | | | | | | | | | | | | | | | | | Just like in (529301c pinctrl: samsung: Parse pin groups before calling pinctrl_register()), Rockchip also needs to parse pin groups earlier to make hogs work. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl: rockchip: Don't call pinctrl_gpio_direction_output() in ↵Doug Anderson2014-10-291-16/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin_config_set() The Rockchip pinctrl driver was calling rockchip_gpio_direction_output() in the pin_config_set() callback. This was just a shortcut for: * rockchip_gpio_set() * pinctrl_gpio_direction_output() Unfortunately it's not so good to call pinctrl_gpio_direction_output() from pin_config_set(). Specifically when initting hogs you'll get an error. Let's refactor a little so we can call _rockchip_pmx_gpio_set_direction() directly. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl: rockchip: Set wake_enabledDoug Anderson2014-10-291-0/+1
|/ | | | | | | | | | | | | The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup the .wake_enabled member. That means that we can never actually use a pin for wakeup. When "irq_set_irq_wake()" tries to call through it will always get a failure from set_irq_wake_real() and will then set wake_depth to 0. Assuming you can resume you'll later get an error message about "Unbalanced IRQ x wake disable". Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'pinctrl-v3.18-1' of ↵Linus Torvalds2014-10-081-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.18 development series: - New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin controllers. - Incremental new features on the Rockchip, atlas 6, OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik. - Push Freescale drivers down into their own subdirectory. - Assorted sprays of syntax and semantic fixes" * tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: specify bindings for pins and groups pinctrl: nomadik: improve GPIO debug prints pinctrl: abx500: refactor DT parser to take two paths pinctrl: abx500: use helpers for map allocation/free pinctrl: alter device tree bindings for functions pinctrl: nomadik: refactor DT parser to take two paths pinctrl: nomadik: use utils map free function pinctrl: nomadik: use util function to reserve maps pinctrl: qcom: use restart_notifier mechanism for ps_hold pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation pinctrl: berlin: fix the dt_free_map function pinctrl: at91: disable PD or PU before enabling PU or PD pinctrl: st: remove gpiochip in failure cases pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add pinctrl: at91: Fix failure path in at91_gpio_probe path pinctrl: lantiq: Release gpiochip resources in fail case pinctrl: imx: detect uninitialized pins pinctrl: tegra: Add MIPI pad control pinctrl: at91: Switch to using managed clk_get pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges ...
| * pinctrl: clean up after enable refactoringLinus Walleij2014-09-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2243a87d90b42eb38bc281957df3e57c712b5e56 "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Fan Wu <fwu@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: fix rk3288 gpio0 configurationSonny Rao2014-08-171-6/+9
|/ | | | | | | | | | | | | | | | | | | On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank. The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add drive-strength control for rk3288Heiko Stübner2014-07-231-0/+112
| | | | | | | | | The rk3288 is the first Rockchip soc handling the drive strength on a per-pin basis, while the older ones can set the drive-strength only for specific pin-groups. Therefore limit setting the drive-strength to this soc for now. Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add separate type for rk3288Heiko Stübner2014-07-231-1/+5
| | | | | | | | An upcoming pinctrl function of the rk3288 differs again from everything else, so we'll need a separate type for it. Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: set is_generic in pinconf_opsHeiko Stübner2014-07-231-0/+1
| | | | | | | | The rockchip pinctrl driver implements the generic pinconfig, therefore also state this, so that the default pinconf dump functions work. Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: remove all usage of gpio_remove ret val in driver/pinctlabdoulaye berthe2014-07-221-12/+4
| | | | | Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add support for rk3288 pin-controllerHeiko Stübner2014-07-111-0/+73
| | | | | | | | The pin-controller of the new RK3288 contains all the quirks just added in the previous patches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: support unrouted iomuxes per bankHeiko Stübner2014-07-111-0/+11
| | | | | | | | | | | On the upcoming RK3288 SoC contain some unrouted pins in their banks. So while for example pin8 of bank5 stays pin8 with all its settings (register offset etc), pins 0 to 7 are not routed outside the SoC at all. Therefore add a flag to mark these unrouted iomuxes to prevent people from using them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: enable iomuxes from pmu spaceHeiko Stübner2014-07-111-12/+30
| | | | | | | | The upcoming rk3288 moves some iomux settings to the pmu register space. Therefore add a flag for this and adapt the mux functions accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add support for 4bit wide iomux settingsHeiko Stübner2014-07-111-8/+26
| | | | | | | | | In the upcoming rk3288 SoC some iomux settings are 4bit wide instead of the regular 2bit. Therefore add a flag to mark iomuxes as such and adapt the mux-access as well as the offset calculation accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: precalculate iomux offsetsHeiko Stübner2014-07-111-11/+45
| | | | | | | | | | An upcoming SoC introduces an interesting quirk to iomux handling making the calculation of the iomux register-offset harder. To keep the complexity down when getting/setting the mux, precalculate the actual register offset at probe-time. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: generalize bank-quirksHeiko Stübner2014-07-111-19/+39
| | | | | | | | | | | | | | Upcoming Rockchip SoCs have additional quirks to handle. Currently they would be handled by giving the bank a special compatible property. But the nature of the new quirks would require a lot of them. Also as we want to move to the separate dw_gpio driver in the future, these bank-definitions should be extended at all. Describing the bank quirks this way also enables us to deprecate the special bank compatible string for bank0 on rk3188 and simplify the handling code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: avoid duplicated calling enable_pinmux_setting for a pinFan Wu2014-07-111-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: base regmap supplied by a sysconHeiko Stübner2014-05-091-19/+28
| | | | | | | | | | | | | This allows the basic registers of the general register files to be supplied by a syscon instead of being mapped locally. The GRF registers contain a lot more than pinctrl functions like dma, usb-phy and general soc control and status registers, intermixed with the iomux, pull and drive-strength registers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: only map bank0-pull-region when pmu regmap missingHeiko Stübner2014-05-091-11/+19
| | | | | | | | | When the pmu registers are supplied through a syscon regmap we do not need to map the registers ourself. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: let pmu registers be supplied by a sysconHeiko Stübner2014-05-091-2/+15
| | | | | | | | | | Currently the pmu registers containing pin pull settings on the rk3188 are mapped locally when bank0 is instantiated. Add an alternative that can resolve the pmu from a syscon phandle. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_dataHeiko Stübner2014-05-091-8/+9
| | | | | | | | | Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because later on we need to check a value from it when registering the gpio banks. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: use regmaps instead of raw mappingsHeiko Stübner2014-05-091-36/+80
| | | | | | | | This allows us to use syscons in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: do not require 2nd register areaHeiko Stübner2014-05-091-3/+12
| | | | | | | | | | | Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handlingHeiko Stübner2014-04-231-0/+40
| | | | | | | | | In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: return a complete config in pinconf_getHeiko Stübner2014-04-231-2/+5
| | | | | | | | | | Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: handle first half of rk3188-bank0 correctlyHeiko Stübner2014-04-141-0/+14
| | | | | | | | | | | The first half of pinbank 0 only has one muxing function (as gpios) and does not have a special mux-register. Therefore ensure that no other mux function can be selected and also do not write to a non-existent register. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add return value to rockchip_set_muxHeiko Stübner2014-04-141-7/+25
| | | | | | | | | In a following change, rockchip_set_mux gets the possibility to fail. Therefore add a return value to it and honor error codes in functions using rockchip_set_mux. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: fix offset of mux registers for rk3188Beniamino Galvani2014-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The correct value of .mux_offset for rk3188 seems to be 0x60 instead of 0x68. Heiko adds: GPIO0 only has the second two IOMUX registers: - GRF_GPIO0C_IOMUX at 0x68 - GRF_GPIO0D_IOMUX at 0x6c which I guess is where my mistake comes from. It looks like there does no iomux register exist at all for the first 16 pins. In any case, the current number is wrong, and the 0x60 offset is the correct one, but I guess we need to determine what the affected pins do - do they always have a gpio mux or such? Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: missing unlock on error in rockchip_set_pull()Dan Carpenter2013-11-251-0/+1
| | | | | | | | | | We need to unlock here before returning -EINVAL. Fixes: 6ca5274d1d12 ('pinctrl: rockchip: add rk3188 specifics') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: testing the wrong variableDan Carpenter2013-11-251-2/+2
| | | | | | | | | There is a copy and paste bug so we test "info->reg_base" instead of "info->reg_pull". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: emulate both edge triggered interruptsHeiko Stübner2013-10-161-7/+54
| | | | | | | | | | | | The gpio interrupt controller on Rockchip socs can do edge triggers only for single edges but not both. Nevertheless a lot of gpio users rely on the availability of both-edge triggered interrupts - i.e. gpio-keys. Therefore implement a solution similar to pinctrl-coh901 re-setting the triggering edge depending on the gpio value in the interrupt demuxer. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add rk3188 specificsHeiko Stübner2013-10-161-7/+112
| | | | | | | | | | | | Besides the pull registers sitting in a separate place, the rk3188 also has the peculiarity that the pull registers of the first bank are split and the first half is sitting in the register space of the pmu. Therefore this adds a special bank-type for the first bank, to handle the two register sources. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: remove redundant checkHeiko Stübner2013-10-161-6/+0
| | | | | | | | | The check limiting bias options to supported ones is already done thru rockchip_pinconf_pull_valid. Therefore this check is redundant and can be removed. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add support for multiple bank typesHeiko Stübner2013-10-161-3/+14
| | | | | | | | | | | There are Rockchip SoCs, namely the rk3188, that combine a set of regular banks with banks that need special handling for some settings. Therefore add the possibility for the driver to handle more than one bank type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: separate different sub-types moreHeiko Stübner2013-10-161-48/+57
| | | | | | | | | | | | | | | | | | Further investigation of the different Rockchip SoCs showed that the differences especially in the pull settings are quite deep. As further patches will show, the register layout for the pulls of the rk3188 is quite strange. Also it is to assume, that later Rockchip SoCs may introduce even more quirks in this regard, making it hard to support all of those using the current generic pull_* variables. Therefore move the driver to hold the type of controller in an enum and do the handling according to it in the necessary places. Also instead of calculating the register in the get and set pull functions move it to a type-specific callback. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: Implement .request() and .free() callbacksAxel Lin2013-08-291-0/+12
| | | | | | | | | | Implement .request() and .free() callbacks on the GPIO chips to inform pinctrl when a GPIO is requested or freed. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Pass all configs to driver on pin_config_set()Sherman Yin2013-08-281-22/+35
| | | | | | | | | | | | | | | | | | | | | When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Matt Porter <matt.porter@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: Simplify pin_to_bank equationAxel Lin2013-08-281-2/+1
| | | | | | | | | | If (b->pin_base + b->nr_pins - 1) < pin is true, pin >= b->pin_base is always true because b->nr_pins is never less than 0. Thus this patch simplify the equation. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: Remove of_match_ptr macro for DT only driverAxel Lin2013-08-281-1/+1
| | | | | | | | This is a DT only driver and rockchip_pinctrl_dt_match is always compiled in. Thus remove of_match_ptr macro. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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