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* pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interruptLad Prabhakar2022-07-101-0/+233
| | | | | | | | | | | | | | Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220707182314.66610-7-prabhakar.mahadev-lad.rj@bp.renesas.com
* Merge tag 'renesas-pinctrl-for-v5.19-tag2' of ↵Linus Walleij2022-05-1435-2497/+1173
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.19 (take two) - Reserved field optimizations, - Miscellaneous fixes and improvements.
| * pinctrl: renesas: checker: Add reserved field checksGeert Uytterhoeven2022-05-051-1/+10
| | | | | | | | | | | | | | | | | | Add checks for discovering registers with reserved fields that could benefit from being described using variable-width reserved field shorthands, reducing kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7786: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-13/+8
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 79 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7785: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-36/+24
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 150 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7757: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-57/+38
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 115 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7734: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-12/+9
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 161 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7724: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-3/+4
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 8 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7723: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-31/+39
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 105 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7722: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-122/+80
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 396 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7720: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-29/+28
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh73a0: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-57/+30
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 154 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7269: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-39/+43
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 406 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7264: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-52/+52
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 572 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7203: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-32/+21
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 281 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-60/+27
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 183 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-131/+72
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 556 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7db3751ecf96fcc469bd14eeb02d69e565956151.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77995: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-85/+22
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 422 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77990: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-92/+29
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 226 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77980: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-63/+28
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 198 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77970: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-93/+29
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 268 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7796: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-105/+32
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 496 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77965: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-105/+32
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 496 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2aff2f4c1ed6d834370ce6dd9379c8c93bfc0a92.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77951: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-105/+32
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 496 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cd59cc2e0f55f0dcede1356f73a9e69fe09bf5eb.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77950: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-103/+28
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 473 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a1617d24af2b9b3224ce84c0ada535565009fdda.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7792: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-106/+35
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 257 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0f211d493a0cfbcd96d84a709d21bea51c7385ae.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7779: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-7/+4
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 81 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ecc7377d2992694226dcf055bed0b617701a3d71.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77470: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-36/+20
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 70 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c5183fcb3dd417d57ced0f60d091e2c7d37e1c8c.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7740: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-35/+39
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 230 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a18fb98a4eefe648a1b1c5b5913dbeee092674c4.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a73a4: Optimize fixed-width reserved fieldsGeert Uytterhoeven2022-05-051-42/+16
| | | | | | | | | | | | | | | | | | | | | | Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 126 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f835c2ff5bb07e541f6377b16f0a32c5aad2a47f.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: sh7734: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-72/+22
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 174 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3ab96d28494b8c5a2d427ba25f31a04ca0cc7305.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a779f0: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-11/+2
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 164 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c98e577996a71ae96145ee6da94aa18fd9ea85b9.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a779a0: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-11/+3
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 140 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/807b2a7e02be2fac50c280961a4841813ab13cd8.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77995: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-20/+4
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 246 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7098704f89bb702c28036c567d3222521ff60f86.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77990: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-7/+4
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c032fce3fff6a6a63dc90f9ab8dfe1f4f3cf6ad6.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77980: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-13/+3
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 168 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c81b26815dff2e191b8c415624a20aa3b4725d23.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77970: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-12/+2
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 164 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f2dda82454bb1b0c97f842de2c9fa68da05ef3e6.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77965: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-21/+8
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 148 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1cf52b1f93e8af593a60f65d8a848d1ebb24cac6.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7796: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-21/+8
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 148 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/433f5ddcc2dba7352825cba007b99b8e654d4c61.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77951: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-23/+9
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 152 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35d0ff4881335889002718540101bcdb8e7f5b5a.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77950: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-31/+8
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 232 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1866c399e94408439a469c12dc53557b55a00f3a.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7794: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-76/+21
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 201 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2fa43bd38c5cf260e89ae1da38d1a217ab762589.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7792: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-74/+16
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 784 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d39a52cf972a450ef5a0989ba7e448115a8147ba.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7791: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-79/+32
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 349 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/972808be595fd742afc6b7fc89751ca4788d6f62.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7790: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-78/+32
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 445 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/842d8060422a9b67dfac4af6d9325d0d99cf50dc.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7779: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-48/+23
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 197 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4b468118e0da681c860ed750976a990a0930dcba.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a7778: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-74/+24
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 142 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1af5225c81ac871a461f7d824619275e2e0ed8df.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: r8a77470: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-46/+8
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 114 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/bc8f9647bbf677ac67cbdb34cf0c8fbaf62fb7fc.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: emev2: Use shorthands for reserved fieldsGeert Uytterhoeven2022-05-051-46/+13
| | | | | | | | | | | | | | | | | | | | Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 769 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/616afe67d3b4d2cbf5f43876f9aa7b258862ceaa.1649865241.git.geert+renesas@glider.be
| * pinctrl: renesas: rmobile: Mark unused PORTCR bits reservedGeert Uytterhoeven2022-05-051-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The PULMD bits and the SEC bit in the PORTCR register descriptions on SH/R-Mobile SoCs are either unused or unsupported. Describe them as reserved bits using a negative field width value, and drop the corresponding dummy enum IDs. This reduces kernel size by 2832 (R-Mobile APE6), 2544 (R-Mobile A1), and/or 3228 (SH-Mobile AG5) bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1b123d8f04c2314d5a7a87004971868ba2176499.1649865241.git.geert+renesas@glider.be
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