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* pinctrl: remove all usage of gpio_remove ret val in driver/pinctlabdoulaye berthe2014-07-221-6/+3
| | | | | Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: sh73a0: Introduce the use of devm_regulator_registerHimangi Saraogi2014-07-111-9/+2
| | | | | | | | | | | This patch moves data allocated using regulator_register to devm_regulator_register and does away the calls to regulator_unregister. The sh73a0_pinmux_soc_exit function is no longer needed and is removed. Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Acked-by: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: r8a7791: add CAN pin groupsSergei Shtylyov2014-07-111-0/+167
| | | | | | | | Add CAN0/1 data/clock pin groups to R8A7791 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: avoid duplicated calling enable_pinmux_setting for a pinFan Wu2014-07-111-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Add HSCIF pin supportNobuhiro Iwamatsu2014-07-111-0/+250
| | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.16-1' of ↵Linus Torvalds2014-06-036-12/+550
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
| * pinctrl: sh-pfc: r8a73a4: Allow Multiplatform BuildMagnus Damm2014-05-231-0/+3
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow r8a73a4 Multiplatform build. Needed to enable r8a73a4 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: sh73a0: Allow Multiplatform BuildMagnus Damm2014-05-231-0/+2
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow sh73a0 Multiplatform build. Needed to enable sh73a0 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7740: Allow Multiplatform BuildMagnus Damm2014-05-231-0/+2
| | | | | | | | | | | | | | | | | | Add #ifdefs to allow r8a7740 Multiplatform build. Needed to enable r8a7740 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatformLaurent Pinchart2014-05-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | In the multiplatform kernel case the IRQs associated with the PFC GPIOs are specified through DT. The pinmux_irq irq field is thus ignored by the code, and doesn't need to be set. This will allow removing the mach/irq.h include from pfc-*.c files that was required for the irq_pin() macro used to initialize the irq field. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pfc: r8a7790: add mux data for IIC(B) coresWolfram Sang2014-04-221-2/+116
| | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pfc: r8a7790: add i2c0 muxingWolfram Sang2014-04-221-1/+21
| | | | | | | | | | | | | | | | | | Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: r8a7791: Add Audio pin supportKuninori Morimoto2014-04-221-0/+61
| | | | | | | | | | | | | | Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: r8a7791: Add SSI pin supportKuninori Morimoto2014-04-221-0/+314
| | | | | | | | | | | | | | Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groupsLaurent Pinchart2014-04-221-10/+27
| | | | | | | | | | | | | | | | | | The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | sh-pfc: r8a7791: Fix definition of MOD_SEL3Phil Edworthy2014-04-231-1/+1
| | | | | | | | | | | | | | | | There is a missing 0 entry from the MOD_SEL3 table. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | sh-pfc: r8a7790: Fix definition of IPSR5Guido Piasenza2014-04-231-2/+1
|/ | | | | | | | | The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.15-1' of ↵Linus Torvalds2014-04-012-0/+767
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
| * pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groupsGeert Uytterhoeven2014-03-051-0/+469
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groupsGeert Uytterhoeven2014-03-051-0/+129
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pfc: r8a7791: add mux data for IIC(B) coresWolfram Sang2014-02-251-0/+64
| | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7790: Add QSPI pin groupsGeert Uytterhoeven2014-02-251-0/+33
| | | | | | | | | | | | | | | | | | | | | | A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUSMagnus Damm2014-02-111-0/+9
| | | | | | | | | | | | | | | | | | | | Create a new group for the USB0 OVC/VBUS pin by itself. This allows us to monitor PWEN as GPIO on the Lager board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7791: Add QSPI pin groupsGeert Uytterhoeven2014-02-101-0/+63
| | | | | | | | | | | | | | | | | | | | A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
* | pinctrl: sh-pfc: r8a7791: SD1_CLK fixMagnus Damm2014-03-051-2/+4
|/ | | | | | | | | | Fix the SD1_CLK handling for r8a7791. Without this patch it is impossible to request all pins needed for SDHI1 on the Koelsch board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.14-1' of ↵Linus Torvalds2014-01-2124-232/+1438
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull bulk pin control changes from Linus Walleij: "This has been queued and tested for a while. Lots of action here, like in the GPIO tree, embedded stuff like this is really hot now it seems. Details in the signed tag. I'm especially happy about the Qualcomm driver as it is used in such a huge subset of mobile handsets out there, and these platforms in general need better upstream support - New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual" * tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sunxi: Honor GPIO output initial vaules pinctrl: capri: add dependency on OF ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Add pinctrl binding for Broadcom Capri SoCs pinctrl: Add void * to pinctrl_pin_desc pinctrl: st: Fix a typo in probe pinctrl: Fix some typos and grammar issues in the documentation pinctrl: sirf: lock IRQs when starting them pinctrl: sirf: put gpio interrupt pin into input status automatically pinctrl: sirf: use only one irq_domain for the whole device node pinctrl: single: fix infinite loop caused by bad mask pinctrl: single: fix pcs_disable with bits_per_mux pinctrl: single: fix DT bindings documentation pinctrl: as3722: Set pin to output mode for some function pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync pinctrl: sirf: fix the pins of sdmmc5 connected with TriG pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6 pinctrl: sunxi: Add Allwinner A20 clock output pin functions pinctrl/lantiq: fix typo ...
| * pinctrl: sh-pfc: r8a7791: Add I2C pinsValentine Barshak2014-01-071-0/+196
| | | | | | | | | | | | | | | | This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7791: Add VIN pinsValentine Barshak2014-01-071-0/+360
| | | | | | | | | | | | | | | | | | | | | | This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins togetherValentine Barshak2014-01-071-28/+12
| | | | | | | | | | | | | | | | | | | | This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux arrayValentine Barshak2014-01-071-1/+1
| | | | | | | | | | | | | | | | This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart2013-12-208-11/+11
| | | | | | | | | | | | | | The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: sh: Constify pins and cfg_regs arraysLaurent Pinchart2013-12-2012-12/+12
| | | | | | | | | | | | | | The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Constify IRQ GPIOs arraysLaurent Pinchart2013-12-202-3/+3
| | | | | | | | | | | | | | The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literalsLaurent Pinchart2013-12-201-4/+5
| | | | | | | | | | | | | | | | | | The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: Support GPIO to IRQ mapping specified IRQ resourcesLaurent Pinchart2013-12-123-17/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: Rename sh_pfc window field to windowsLaurent Pinchart2013-12-127-20/+21
| | | | | | | | | | | | | | | | There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: sh73a0: Sort IRQ entries by IRQ numberLaurent Pinchart2013-12-121-24/+23
| | | | | | | | | | | | | | | | | | This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: sh73a0: Add missing IRQ15Laurent Pinchart2013-12-121-0/+1
| | | | | | | | | | | | | | | | The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: Terminate gpios array by -1Laurent Pinchart2013-12-122-4/+4
| | | | | | | | | | | | | | | | | | 0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: Turn unsigned indices into unsigned intLaurent Pinchart2013-12-122-5/+5
| | | | | | | | | | | | | | | | Some indices take positive values only, make them unsigned. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pinsValentine Barshak2013-12-101-0/+168
| | | | | | | | | | | | | | | | | | There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pinsValentine Barshak2013-12-101-8/+104
| | | | | | | | | | | | | | | | | | Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pinsValentine Barshak2013-12-101-30/+95
| | | | | | | | | | | | | | | | | | | | | | | | This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC togetherValentine Barshak2013-12-101-12/+6
| | | | | | | | | | | | | | | | This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groupsValentine Barshak2013-12-101-16/+16
| | | | | | | | | | | | | | | | This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * sh-pfc: r8a7791: Fix msiof groups to follow GROUPTakashi Yoshii2013-12-101-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: r8a7790: Add Audio pin supportKuninori Morimoto2013-12-101-0/+68
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: r8a7790: Add SSI pin supportKuninori Morimoto2013-12-101-0/+239
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: Share common PORTCR macro definitionLaurent Pinchart2013-12-105-45/+1
| | | | | | | | | | | | | | | | The macro is defined identically in four different locations. Share it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: r8a7791: Fix DU pin groups organisationLaurent Pinchart2013-11-251-9/+27
| | | | | | | | | | | | | | | | | | | | Rename the sync_1 group to sync as the device has a single sync pin group for the DU, move the cde_disp mux array right after the corresponding pins array, and split the clk_in pins in three separate groups as the pins can be used independently. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 11:58:08 +0100