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* Merge tag 'sh-pfc-for-v4.11-tag2' of ↵Linus Walleij2017-01-301-0/+86
|\ | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.11 (take two) - Add Gyro-ADC pin groups for R-Car M2-W.
| * pinctrl: sh-pfc: r8a7791: Add ADI pinconf supportJacopo Mondi2017-01-201-0/+86
| | | | | | | | | | | | | | | | Add pin configuration support for Gyro-ADC, named ADI on r8a7791 SoC. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge tag 'sh-pfc-for-v4.11-tag1' of ↵Linus Walleij2017-01-133-213/+2158
|\| | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.11 - Add bias handling for non-GPIO pins for R-Car H3, - Add drive-strength and bias handling for R-Car M3-W, - Add CAN, CAN FD, MSIOF, and HSCIF pin groups for R-Car M3-W, - Add SDHI voltage switching for R-Car M2-N.
| * pinctrl: sh-pfc: r8a7796: Add HSCIF pins, groups, and functionsUlrich Hecht2016-12-271-0/+283
| | | | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7793: Implement voltage switching for SDHISimon Horman2016-12-271-0/+1
| | | | | | | | | | | | | | | | Voltage switching is the same as on the r8a7791. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and functionsTakeshi Kihara2016-12-271-0/+913
| | | | | | | | | | | | | | | | | | This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 SS1_E/SS2_E pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add CAN FD supportChris Paterson2016-12-271-0/+37
| | | | | | | | | | | | | | | | | | This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add CAN supportChris Paterson2016-12-271-0/+52
| | | | | | | | | | | | | | | | | | This patch adds CAN[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias settingNiklas Söderlund2016-12-271-201/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the bias to be configured. Add those pins to the list of pins and to the bias configuration array. The pins can now be referred to in DT by function names and their bias setting set. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add bias pinconf supportNiklas Söderlund2016-12-271-39/+315
| | | | | | | | | | | | | | | | Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add drive strength supportNiklas Söderlund2016-12-271-12/+347
| | | | | | | | | | | | | | | | | | Define the drive strength registers for the R8A7796. Add pins which are not part of a GPIO bank nor can be muxed between different functions but which still allow for their drive-strength to be configured. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | pinctrl: core: Fix regression caused by delayed work for hogsTony Lindgren2017-01-131-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit df61b366af26 ("pinctrl: core: Use delayed work for hogs") caused a regression at least with sh-pfc that is also a GPIO controller as noted by Geert Uytterhoeven <geert@linux-m68k.org>. As the original pinctrl_register() has issues calling pin controller driver functions early before the controller has finished registering, we can't just revert commit df61b366af26. That would break the drivers using GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. So let's fix the issue with the following steps as a single patch: 1. Revert the late_init parts of commit df61b366af26. The late_init clearly won't work and we have to just give up on fixing pinctrl_register() for GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. 2. Split pinctrl_register() into two parts By splitting pinctrl_register() into pinctrl_init_controller() and pinctrl_create_and_start() we have better control over when it's safe to call pinctrl_create(). 3. Introduce a new pinctrl_register_and_init() function As suggested by Linus Walleij <linus.walleij@linaro.org>, we can just introduce a new function for the controllers that need pinctrl_create() called later. 4. Convert the four known problem cases to use new function Let's convert pinctrl-imx, pinctrl-single, sh-pfc and ti-iodelay to use the new function to fix the issues. The rest of the drivers can be converted later. Let's also update Documentation/pinctrl.txt accordingly because of the known issues with pinctrl_register(). Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pinsNiklas Söderlund2016-11-161-0/+69
| | | | | | | | | Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other than QSPI, but their drive strength can be controlled. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pinsNiklas Söderlund2016-11-161-3/+27
| | | | | | | | | | | | | | Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable ↵Niklas Söderlund2016-11-161-15/+148
| | | | | | | | | | | | | | | drive-strength There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT by function names and their drive-strength modified. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Support named pins with custom configurationNiklas Söderlund2016-11-161-0/+8
| | | | | | | | | | | | | | | Pins not associated with a GPIO port can still have other configuration parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named pins to be declared with a set of configurations. The new macro is an modification of SH_PFC_PIN_NAMED to allow for optional configuration to be assigned. The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be used to define pins not associated with a GPIO port. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7778: Use lookup function for bias dataNiklas Söderlund2016-11-161-170/+172
| | | | | | | | | | Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Use lookup function for bias dataNiklas Söderlund2016-11-161-171/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Simplify get bias logicNiklas Söderlund2016-11-161-6/+5
| | | | | | | | | | The last else statement is missing braces, and the indentation level can be reduced. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Add helper to handle bias lookup tableNiklas Söderlund2016-11-153-0/+25
| | | | | | | | | | | | | | | | On some SoC there are no simple mapping of pins to bias register bits and a lookup table is needed. This logic is already implemented in some SoC specific drivers that could benefit from a generic implementation. Add helpers to deal with the lookup which later can be used by the SoC specific drivers. The logic used to lookup are different from the one it aims to replace, this is intentional. This new method reduces the memory consumption at the cost of increased CPU usage and fix a bug where a WARN() would incorrectly be triggered if the register offset is 0. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLENiklas Söderlund2016-11-151-1/+2
| | | | | | | | | | | | | | | | | | | Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if the operation get_bias() is implemented but the pin is not handled by the get_bias() implementation. In that case the output will state that "input bias disabled" indicating that this pin has bias control support. Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also solves the issue where SoC specific implementations print error messages if their particular implementation of {set,get}_bias() is called with a pin it does not know about. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add DU supportNiklas Söderlund2016-11-151-0/+101
| | | | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Based on a similar patch from Laurent Pinchart for the r8a7795 PFC driver. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functionsTakeshi Kihara2016-11-151-0/+87
| | | | | | | | | This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS, AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Fix GPSR definitions for SDHI2/3Geert Uytterhoeven2016-11-071-10/+10
| | | | | | | | | | | Fix off-by-one (row and/or register) errors in links to Peripheral Function Select Register bitfields from GPIO/Peripheral Function Select Register 4 macros for SDHI2 and SDHI3 pins. Based on rev. 0.52E of the R-Car Gen3 User's Manual. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
* pinctrl: sh-pfc: r8a7796: Add DRIF supportRamesh Shanmugasundaram2016-10-171-0/+291
| | | | | | | This patch adds DRIF[0-3] pinmux support for r8a7796 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add I2C pin supportUlrich Hecht2016-10-171-0/+77
| | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHISimon Horman2016-09-141-1/+27
| | | | | | | | | | | | All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHISimon Horman2016-09-141-1/+28
| | | | | | | | | | | | All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Add PORT_GP_24 helper macroSimon Horman2016-09-141-2/+6
| | | | | | | | | This follows the style of existing PORT_GP_X macros and will be used by a follow-up patch for the r8a7791 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHISimon Horman2016-09-121-2/+26
| | | | | | | | | | | | | | This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Return pinconf with arguments in packed formatNiklas Söderlund2016-09-121-3/+5
| | | | | | | | | | | | | | | | | | | The pinconf-generic code expects configurations with arguments to be returned in a packed format in order to be displayed properly by pinconf_generic_dump_one(). Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on r8a7795/salvator-x now shows: pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector) Instead of: pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector) Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add MSIOF pin groupsSergei Shtylyov2016-09-121-0/+82
| | | | | | | | | | Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add QSPI pin groupsSergei Shtylyov2016-09-121-0/+33
| | | | | | | | | | | Add QSPI pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functionsTakeshi Kihara2016-08-191-0/+275
| | | | | | | | This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functionsTakeshi Kihara2016-08-191-0/+300
| | | | | | | | This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Initial R8A7796 PFC supportTakeshi Kihara2016-08-195-0/+2085
| | | | | | | | | This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add DU supportLaurent Pinchart2016-08-161-0/+100
| | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add DU pin groupsSergei Shtylyov2016-08-081-0/+144
| | | | | | | Add DU pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add VIN pin groupsSergei Shtylyov2016-08-081-0/+577
| | | | | | | | Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Fix VI1_D14_G6_Y6 and VI1_D15_G7_Y7 pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795Geert Uytterhoeven2016-08-081-1/+1
| | | | | | | | This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7792: Add CAN pin groupsSergei Shtylyov2016-08-081-0/+37
| | | | | | | Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add SDHI pin groupsSergei Shtylyov2016-08-081-0/+51
| | | | | | | | Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groupsSergei Shtylyov2016-08-081-0/+99
| | | | | | | Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Add R8A7792 PFC supportSergei Shtylyov2016-08-085-6/+1747
| | | | | | | | | Add the PFC support for the R8A7792 SoC including pin groups for some on-chip devices such as SCIF, INTC, and LBSC... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: s/LSBC/LBSC/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Fix overly long linesSergei Shtylyov2016-08-081-40/+55
| | | | | | | | | The PORT_GP_CFG_<n>() macros take up more than 80 columns -- and not for a good reason. Make the header file checkpatch.pl-proof at least in this respect... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add bias pinconf supportUlrich Hecht2016-08-081-12/+242
| | | | | | | | Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the codeWei Yongjun2016-07-111-4/+1
| | | | | | | | Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7795: Add DRIF supportRamesh Shanmugasundaram2016-06-231-0/+291
| | | | | | | This patch adds DRIF[0-3] pinmux support for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Use PINMUX_SINGLE() for I2CKuninori Morimoto2016-06-231-5/+3
| | | | | | | | Now we have PINMUX_SINGLE(). Let's use it instead of PINMUX_IPSR_NOGP() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Convert to devm_gpiochip_add_data()Geert Uytterhoeven2016-06-214-26/+1
| | | | | | | | | This allows to remove the .remove() callback, and all functions and data it needed for its own bookkeeping. Suggested-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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