Commit message (Collapse) | Author | Age | Files | Lines | |
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* | pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl | Icenowy Zheng | 2017-08-22 | 1 | -3/+23 |
| | | | | | | | | | | | | | | | | The pin controller of Allwinner H5 has three IRQ banks, however in old versions of drivers and device trees, only two are set, which makes PG bank IRQ not available. If it's directly set to 3, the old device trees will fail to boot. Add a workaround (and a warning) for older device trees, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | ||||
* | drivers: pinctrl: add driver for Allwinner H5 SoC | Icenowy Zheng | 2017-01-30 | 1 | -0/+558 |
Based on the Allwinner H5 datasheet and the pinctrl driver of the backward-compatible H3 this introduces the pin multiplex assignments for the H5 SoC. H5 introduced some more pin functions (e.g. three more groups of TS pins, and one more groups of SIM pins) than H3. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |