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* Merge tag 'pinctrl-v6.7-1' of ↵Linus Torvalds2023-11-041-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No pin control core changes this time. New drivers: - Realtek RTD family pin control driver and RTD1619B, RTD1319D and RTD1315E subdrivers - Nuvoton NPCM8xx combined pin control and GPIO driver - Amlogic T7 pin control driver - Renesas RZ/G3S pin control driver Improvements: - A number of additional UART groups added to the Mediatek MT7981 driver - MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660 - Extra GPIO banks for the Sunxi H616 - MLSP I2C6 function support in Qualcomm MSM8226 - Some __counted_by() annotations for dynamic arrays - Ongoing work to make remove() return void - LSBC groups and functions in the Renesas R8A7778" * tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: Use device_get_match_data() dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes dt-bindings: pinctrl: brcm: Ensure all child node properties are documented pinctrl: renesas: rzn1: Convert to platform remove callback returning void pinctrl: renesas: rzg2l: Add RZ/G3S support dt-bindings: pinctrl: renesas: Document RZ/G3S SoC pinctrl: renesas: rzg2l: Add support for different DS values on different groups pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets pinctrl: renesas: rzg2l: Index all registers based on port offset pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions pinctrl: intel: fetch community only when we need it pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case pinctrl: cherryview: Convert to platform remove callback returning void pinctrl: sprd-sc9860: Convert to platform remove callback returning void pinctrl: qcom/msm: Convert to platform remove callback returning void pinctrl: qcom/lpi: Convert to platform remove callback returning void ...
| * pinctrl: tegra: add OF node when logging OF parsing errorsLuca Ceresoli2023-09-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | These errors are not quite clear without also logging they device tree node being parsed, especially when the pinmux node has lots of subnodes. Adding the node name helps a lot in finding the node that triggers the error. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230926103938.334055-1-luca.ceresoli@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Revert "pinctrl: tegra: Add support to display pin function"Linus Walleij2023-09-272-19/+2
|/ | | | | | | | | | This reverts commit d1cd5b51bc9152dc2b63c5f843590272d6694d50. It was reported that some I2C3 functions stop working after this patch, and it is just debug help so let's revert it and investigate. Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'intel-pinctrl-v6.6-1' of ↵Linus Walleij2023-08-252-5/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.6-1 * New library driver for Intel MID to deduplicate code (Raag Jadav) * Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav) * Move most of the exported functions to the PINCTRL_INTEL namespace * Make use of pm_ptr() in Bay Trail and Lynxpoint drivers * Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers * Consolidata ACPI dependency in Kconfig (Raag Jadav) * Fix address_space_handler() argument in Cherryview driver (Raag Jadav) * Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav) The following is an automated git shortlog grouped by driver: at91: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper baytrail: - Make use of pm_ptr() - reuse common functions from pinctrl-intel - consolidate common mask operation cherryview: - fix address_space_handler() argument - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper - reuse common functions from pinctrl-intel intel: - consolidate ACPI dependency - Switch to use exported namespace - export common pinctrl functions lynxpoint: - Make use of pm_ptr() - reuse common functions from pinctrl-intel Merge patch series: - Merge patch series "Introduce Intel Tangier pinctrl driver" - Merge patch series "Reuse common functions from pinctrl-intel" merrifield: - Adapt to Intel Tangier driver moorefield: - Adapt to Intel Tangier driver mvebu: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: - Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper renesas: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper tangier: - Introduce Intel Tangier driver tegra: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko2023-08-212-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that, make sure the PM ops are used only in CONFIG_PM_SLEEP=y case by wrapping them in pm_sleep_ptr() macro. Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230717172821.62827-11-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | pinctrl: Explicitly include correct DT includesRob Herring2023-07-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: Add support to display pin functionPrathamesh Shete2023-07-202-2/+19
|/ | | | | | | | | | | The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: avoid duplicate field initializersArnd Bergmann2023-06-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The drv_reg field is initialized both in the DRV_PINGROUP_ENTRY_N/DRV_PINGROUP_ENTRY_Y macros and in DRV_PINGROUP_Y. Since each pingroup expands both macros, the are always duplicate and turning on -Woverride-init (which is disabled by default) causes a huge amount of warnings like: drivers/pinctrl/tegra/pinctrl-tegra234.c:1384:27: error: initialized field overwritten [-Werror=override-init] 1384 | #define DRV_PINGROUP_Y(r) ((r)) | ^ drivers/pinctrl/tegra/pinctrl-tegra234.c:1397:28: note: in expansion of macro 'DRV_PINGROUP_Y' 1397 | .drv_reg = DRV_PINGROUP_Y(r), \ | ^~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra234.c:1447:49: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1447 | #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ ... Remove the intialization that is never used here. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230616161603.1127687-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add Tegra234 pinmux driverPrathamesh Shete2023-06-093-0/+1966
| | | | | | | | | | This change adds support for the two pin controllers found on Tegra234. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230605154230.2910847-3-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Consistently refer to SoC dataThierry Reding2023-06-011-7/+6
| | | | | | | | | | | The SoC-specific data is stored in pmx->soc and that's used throughout the driver to access this data. The probe function has access to a local version of that copy and uses it in some occasions. Replace them with the more standard pmx->soc access for more consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230530105308.1292852-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Duplicate pinmux functions tableThierry Reding2023-06-018-35/+25
| | | | | | | | | | | | | | | The function table is filled with group information based on other instance-specific data at runtime. However, the function table can be shared between multiple instances, causing the ->probe() function for one instance to overwrite the table of a previously probed instance. Fix this by sharing only the function names and allocating a separate function table for each instance. Fixes: 5a0047360743 ("pinctrl: tegra: Separate Tegra194 instances") Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230530105308.1292852-1-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Separate Tegra194 instancesThierry Reding2022-11-143-148/+173
| | | | | | | | | | | | | Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add missing header(s)Andy Shevchenko2022-10-242-4/+9
| | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* pinctrl: tegra: tegra194: drop unused pin groupsKrzysztof Kozlowski2022-05-041-9/+0
| | | | | | | | | | | | | | | | | The sdmmc1_hv_trim_pins, sdmmc3_hv_trim_pins and sys_reset_n_pins are not defined as pin groups: drivers/pinctrl/tegra/pinctrl-tegra194.c:1119:27: error: ‘sdmmc3_hv_trim_pins’ defined but not used [-Werror=unused-const-variable=] 1119 | static const unsigned int sdmmc3_hv_trim_pins[] = { Proper fix would be to define them, but this requires knowledge from datasheet. Removal should not cause any harm and at least it silences the warnings. Fixes: 613c0826081b ("pinctrl: tegra: Add pinmux support for Tegra194") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220429061332.25135-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra194: remove duplicate initializer againArnd Bergmann2021-11-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An earlier bugfix removed a duplicate field initializer in a macro, but it seems that this came back with the following update: drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: error: initialized field overwritten [-Werror=override-init] 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: note: (near initialization for 'tegra194_groups[0].drv_reg') 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ Remove it again. Fixes: 613c0826081b ("pinctrl: tegra: Add pinmux support for Tegra194") Fixes: 92cadf68e50a ("pinctrl: tegra: pinctrl-tegra194: Do not initialise field twice") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211104133645.1186968-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Return const pointer from tegra_pinctrl_get_group()Prathamesh Shete2021-11-161-2/+2
| | | | | | | | | | Instead of returning const pointer from tegra_pinctrl_get_group() the return value is being casted. This change helps return const pointer. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Fix warnings and errorPrathamesh Shete2021-10-261-3/+2
| | | | | | | | Fix warnings are errors caused by commit a42c7d95d29e ("pinctrl: tegra: Use correct offset for pin group"). Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Use correct offset for pin groupPrathamesh Shete2021-10-261-2/+31
| | | | | | | | | | | | | | | Function tegra_pinctrl_gpio_request_enable() and tegra_pinctrl_gpio_disable_free() uses pin offset instead of group offset, causing the driver to use wrong offset to enable gpio. Add a helper function tegra_pinctrl_get_group() to parse the pin group and determine correct offset. Signed-off-by: Kartik K <kkartik@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211025110959.27751-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add pinmux support for Tegra194Prathamesh Shete2021-10-241-35/+1759
| | | | | | | | This change adds pinmux table entries for Tegra194 Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: include lpdr pin propertiesSuresh Mangipudi2021-10-242-164/+168
| | | | | | | | | | | | Update lpdr pin-property for supported pins. lpdr property help disable most basic driver fingers leaving only minimal base driver finger. Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.9-1' of ↵Linus Torvalds2020-08-091-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of the pin control changes for the v5.9 kernel series: Core changes: - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range() macro" was put in an immutable branch and merged into the pinctrl tree as well. We see these changes also here. - Improved debug output for pins used as GPIO. New drivers: - Ocelot Sparx5 SoC driver. - Intel Emmitsburg SoC subdriver. - Intel Tiger Lake-H SoC subdriver. - Qualcomm PM660 SoC subdriver. - Renesas SH-PFC R8A774E1 subdriver. Driver improvements: - Linear improvement and cleanups of the Intel drivers for Cherryview, Lynxpoint, Baytrail etc. Improved locking among other things. - Renesas SH-PFC has added support for RPC pins, groups, and functions to r8a77970 and r8a77980. - The newere Freescale (now NXP) i.MX8 pin controllers have been modularized. This is driven by the Google Android GKI initiative I think. - Open drain support for pins on the Qualcomm IPQ4019. - The Ingenic driver can handle both edges IRQ detection. - A big slew of documentation fixes all over the place. - A few irqchip template conversions by yours truly. * tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC pinctrl: stmfx: Use irqchip template pinctrl: amd: Use irqchip template pinctrl: mediatek: fix build for tristate changes pinctrl: samsung: Use bank name as irqchip name pinctrl: core: print gpio in pins debugfs file pinctrl: mediatek: add mt6779 eint support pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API pinctrl: mcp23s08: Use irqchip template pinctrl: sx150x: Use irqchip template dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes pinctrl: intel: Add Intel Emmitsburg pin controller support pinctl: ti: iodelay: Replace HTTP links with HTTPS ones Revert "gpio: omap: handle pin config bias flags" pinctrl: single: Use fallthrough pseudo-keyword pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword pinctrl: baytrail: Use fallthrough pseudo-keyword ...
| * pinctrl: tegra: pinctrl-tegra194: Do not initialise field twiceLee Jones2020-07-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both PIN_PINGROUP_ENTRY_Y() and DRV_PINGROUP_ENTRY_Y() macros are called for each of the 2 pin groups defined here, and both of them initialise 'drv_reg', causing the compiler to complain. Only initialise 'drv_reg' once. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: warning: initialized field overwritten [-Woverride-init] 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:105:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 105 | DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_clkreq_n_pgg0’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:128:2: note: in expansion of macro ‘PINGROUP’ 128 | PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: note: (near initialization for ‘tegra194_groups[0].drv_reg’) 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:105:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 105 | DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_clkreq_n_pgg0’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:128:2: note: in expansion of macro ‘PINGROUP’ 128 | PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: warning: initialized field overwritten [-Woverride-init] 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:107:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 107 | DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_rst_n_pgg1’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:130:2: note: in expansion of macro ‘PINGROUP’ 130 | PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: note: (near initialization for ‘tegra194_groups[1].drv_reg’) 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:107:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 107 | DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_rst_n_pgg1’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:130:2: note: in expansion of macro ‘PINGROUP’ 130 | PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, | ^~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-23-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: Use noirq suspend/resume callbacksVidya Sagar2020-06-161-2/+2
|/ | | | | | | | | | | Use noirq suspend/resume callbacks as other drivers which implement noirq suspend/resume callbacks (Ex:- PCIe) depend on pinctrl driver to configure the signals used by their respective devices in the noirq phase. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200604174935.26560-1-vidyas@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix several typosDejin Zheng2020-04-281-1/+1
| | | | | | | | | | | use codespell to fix lots of typos over frontends. Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> CC: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200421142402.9524-1-zhengdejin5@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add SFIO/GPIO programming on Tegra194Thierry Reding2020-03-273-0/+51
| | | | | | | | | | | | Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Renumber the GG.0 and GG.1 pinsThierry Reding2020-03-271-7/+4
| | | | | | | | | | There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Do not add default pin range on Tegra194Thierry Reding2020-03-272-2/+1
| | | | | | | | | | | On Tegra194, almost all of the pin control programming happens in early boot firmware, so there is no use in having a pin range defined for all the pins. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Pass struct tegra_pmx for pin range checkThierry Reding2020-03-271-3/+3
| | | | | | | | | | | Pass the struct tegra_pmx when checking for the pin range in device tree. This makes the call site a bit easier to read and will help keep that readability in a subsequent patch. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-7-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typoThierry Reding2020-03-271-1/+1
| | | | | | | | | Properly spell "Schmitt" in the kerneldoc for pin group definitions. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Fix whitespace issues for improved readabilityThierry Reding2020-03-271-16/+17
| | | | | | | | | Fix a few whitespace inconsistencies to make the code easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-5-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: fix missing __iomem in suspend/resumeBen Dooks (Codethink)2020-01-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The functions should have __iomem on the register pointer so add that to silence the following sparse warnings: drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: got void [noderef] <asn:2> * drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: expected void const volatile [noderef] <asn:2> *addr drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: got unsigned int [usertype] * drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: got void [noderef] <asn:2> * drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: expected void volatile [noderef] <asn:2> *addr drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: got unsigned int [usertype] * Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-11-052-5/+2
| | | | | | | | | | | | | | | devm_platform_ioremap_resource() internally have platform_get_resource() and devm_ioremap_resource() in it. So instead of calling them separately use devm_platform_ioremap_resource() directly. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: xusb: Add note about legacy statusThierry Reding2019-10-041-0/+6
| | | | | | | | | | Add a comment about why the call to of_match_node() cannot be replaced by of_device_get_match_data(). This will hopefully prevent people from attempting to clean this up in the future. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Flush pinctrl writes during resumeSowjanya Komatineni2019-08-211-0/+4
| | | | | | | | | | | | This patch adds pinctrl register read to flush all the prior pinctrl writes and then adds barrier for pinctrl register read to complete during resume to make sure all pinctrl changes are effective. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Fix write barrier placement in pmx_writelSowjanya Komatineni2019-08-211-1/+3
| | | | | | | | | | | | | | | pmx_writel uses writel which inserts write barrier before the register write. This patch has fix to replace writel with writel_relaxed followed by a readback and memory barrier to ensure write operation is completed for successful pinctrl change. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1565984527-5272-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra210: Add Tegra210 pinctrl pm opsSowjanya Komatineni2019-08-051-0/+1
| | | | | | | | This patch adds suspend and resume functionality to Tegra210 pinctrl. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add suspend and resume supportSowjanya Komatineni2019-08-052-0/+62
| | | | | | | | | | | | | | This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.3-1' of ↵Linus Torvalds2019-07-1410-56/+241
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
| * pinctrl: tegra: Add bitmask support for parked bitsThierry Reding2019-06-258-47/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Set specific GPIO compatible stringThierry Reding2019-06-253-3/+3
| | | | | | | | | | | | | | | | | | | | | | Rather than reuse the nvidia,tegra30-gpio compatible string to find the GPIO controller on Tegra30, Tegra114, Tegra124 and Tegra210, use the most specific compatible string for each SoC generation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Add Tegra194 pinmux driverKrishna Yarlagadda2019-06-013-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Support 32 bit register accessKrishna Yarlagadda2019-06-012-8/+8
| | | | | | | | | | | | | | | | | | | | Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-058-72/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
|/ | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* pinctrl: tegra: do not export tegra_pinctrl_probeStefan Agner2018-09-201-1/+0
| | | | | | | | No user of tegra_pinctrl_probe can be built as a module, hence exporting the symbol is not necessary. Drop EXPORT_SYMBOL_GPL. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Move drivers registration to arch_init levelDmitry Osipenko2018-08-035-5/+30
| | | | | | | | | | | | | | | | | There is a bug in regards to deferred probing within the drivers core that causes GPIO-driver to suspend after its users. The bug appears if GPIO-driver probe is getting deferred, which happens after introducing dependency on PINCTRL-driver for the GPIO-driver by defining "gpio-ranges" property in device-tree. The bug in the drivers core is old (more than 4 years now) and is well known, unfortunately there is no easy fix for it. The good news is that we can workaround the deferred probe issue by changing GPIO / PINCTRL drivers registration order and hence by moving PINCTRL driver registration to the arch_init level and GPIO to the subsys_init. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: define GPIO compatible node per SoCStefan Agner2018-07-297-3/+9
| | | | | | | | | | | | | Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* treewide: devm_kzalloc() -> devm_kcalloc()Kees Cook2018-06-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
* pinctrl: tegra20: Provide CDEV1/2 clock muxesDmitry Osipenko2018-05-163-12/+40
| | | | | | | | | | | | | | Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Delete two error messages for a failed memory allocation in ↵Markus Elfring2018-01-031-6/+3
| | | | | | | | | | | tegra_pinctrl_probe() Omit extra messages for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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