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* pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20Masahiro Yamada2017-06-201-189/+194
| | | | | | | | | The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 336306ee1f2d ("pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11Masahiro Yamada2017-06-201-172/+192
| | | | | | | | | The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.12-1' of ↵Linus Torvalds2017-05-0311-114/+61
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.12 cycle. The extra week before the merge window actually resulted in some of the type of fixes that usually arrive after the merge window already starting to trickle in from eager developers using -next, I'm impressed. I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal with the onset of Samsung patches. It works great. Apart from that it is a boring round, just incremental updates and fixes all over the place, no serious core changes or anything exciting like that. The most pleasing to see is Julia Cartwrights work to audit the irqchip-providing drivers for realtime locking compliance. It's one of those "I should really get around to looking into that" things that have been on my TODO list since forever. Summary: Core changes: - add bi-directional and output-enable pin configurations to the generic bindings and generic pin controlling core. New drivers or subdrivers: - Armada 37xx SoC pin controller and GPIO support. - Axis ARTPEC-6 SoC pin controller support. - AllWinner A64 R_PIO controller support, and opening up the AllWinner sunxi driver for ARM64 use. - Rockchip RK3328 support. - Renesas R-Car H3 ES2.0 support. - STM32F469 support in the STM32 driver. - Aspeed G4 and G5 pin controller support. Improvements: - a whole slew of realtime improvements to drivers implementing irqchips: BCM, AMD, SiRF, sunxi, rockchip. - switch meson driver to get the GPIO ranges from the device tree. - input schmitt trigger support on the Rockchip driver. - enable the sunxi (AllWinner) driver to also be used on ARM64 silicon. - name the Qualcomm QDF2xxx GPIO lines. - support GMMR GPIO regions on the Intel Cherryview. This fixes a serialization problem on these platforms. - pad retention support for the Samsung Exynos 5433. - handle suspend-to-ram in the AT91-pio4 driver. - pin configuration support in the Aspeed driver. Cleanups: - the final name of Rockchip RK1108 was RV1108 so rename the driver and variables to stay consistent" * tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl: mediatek: Add missing pinctrl bindings for mt7623 pinctrl: artpec6: Fix return value check in artpec6_pmx_probe() pinctrl: artpec6: Remove .owner field for driver pinctrl: tegra: xusb: Silence sparse warnings ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller" pinctrl: make artpec6 explicitly non-modular pinctrl: aspeed: g5: Add pinconf support pinctrl: aspeed: g4: Add pinconf support pinctrl: aspeed: Add core pinconf support pinctrl: aspeed: Document pinconf in devicetree bindings pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl pinctrl: stm32: Add STM32F469 MCU support Documentation: dt: Remove ngpios from stm32-pinctrl binding pinctrl: stm32: replace device_initcall() with arch_initcall() pinctrl: stm32: add possibility to use gpio-ranges to declare bank range pinctrl: armada-37xx: Add gpio support pinctrl: armada-37xx: Add pin controller support for Armada 37xx pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers pinctrl: core: Make pinctrl_init_controller() static pinctrl: generic: Add bi-directional and output-enable ...
| * pinctrl: uniphier: make drivers non-modularMasahiro Yamada2017-03-239-72/+38
| | | | | | | | | | | | | | | | At first these drivers were written as tristate, but the module usecases are actually not tested. Make all of them boolean. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: remove obsoleted compatiblesMasahiro Yamada2017-03-238-42/+23
| | | | | | | | | | | | | | | | | | | | Since commit 3e030b0b4e46 ("pinctrl: uniphier: allow to have pinctrl node under syscon node"), this driver has kept compatibility for the old DT files. Several releases have passed since then, so remove the obsoleted compatibles and clean up the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: uniphier: change pin names of aio/xirq for LD11Kunihiko Hayashi2017-03-061-6/+6
|/ | | | | | | | | This patch changes pin names of AIO and XIRQ according to updated specification. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v4.10-rc6' into develLinus Walleij2017-01-301-1/+1
|\ | | | | | | | | | | | | | | Linux 4.10-rc6 Resolved conflicts in: drivers/pinctrl/pinctrl-amd.c drivers/pinctrl/samsung/pinctrl-exynos.c
| * pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20Masahiro Yamada2017-01-191-1/+1
| | | | | | | | | | | | | | | | Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins. Fixes: 1e359ab1285e ("pinctrl: uniphier: add Ethernet pin-mux settings") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Widen the generic pinconf argument from 16 to 24 bitsMika Westerberg2017-01-261-2/+2
|/ | | | | | | | | | | | | | | | | | | | The current pinconf packed format allows only 16-bit argument limiting the maximum value 65535. For most types this is enough. However, debounce time can be in range of hundreths of milliseconds in case of mechanical switches so we cannot represent the worst case using the current format. In order to support larger values change the packed format so that the lower 8 bits are used as type which leaves 24 bits for the argument. This allows representing values up to 16777215 and debounce times up to 16 seconds. We also convert the existing users to use 32-bit integer when extracting argument from the packed configuration value. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-117-0/+109
| | | | | | | | | | | | | | | Add the following Ethernet interfaces: PH1-LD4: MII, RMII PH1-Pro4: MII, RMII, RGMII PH1-sLD8: MII, RMII (Built-in PHY is also supported) ProXstream2: MII, RMII, RGMII PH1-LD6b: RMII, RGMII PH1-LD11: RMII (Built-in PHY is also supported) PH1-LD20: RMII, RGMII Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11Masahiro Yamada2016-07-041-10/+0
| | | | | | | | | This SoC has no SD card controller. Nor does it have USB port3. These pin-mux settings have no point. Fixes: 70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix meaningless drive control offsetsMasahiro Yamada2016-06-181-3/+3
| | | | | | | | These are input-only pins. They do not support drive controlling in the first place. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: prohibit drive control for pin 61-66 of PH1-LD11Masahiro Yamada2016-06-181-6/+6
| | | | | | | | | According to the hardware document, setting the drive control is prohibited for these pins (N-channel Open Drain pins). Set their drive control attribute to "fixed". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix NAND pin-mux settings for PH1-LD11/LD20Masahiro Yamada2016-06-082-2/+2
| | | | | | | My mistake in the initial support patches. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-05-313-0/+1042
| | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-05-313-6/+967
| | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD11 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-05-317-9/+35
| | | | | | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. To allow to migrate to the new DT structure, this commit adds new compatible strings to not disturb the existing DT. After a while, the old binding will be removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add System Bus pin-mux settingsMasahiro Yamada2016-05-316-0/+166
| | | | | | | This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add dedicated pins to pin tables of PH1-LD4/sLD8Masahiro Yamada2016-05-312-0/+77
| | | | | | | | These pins do not support pin-muxing, but it is useful to support pin configuration for them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-05-318-147/+144
| | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-05-312-11/+14
| | | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit updates the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-05-318-31/+34
| | | | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding the new one. Having just one flag would be better than adding a new struct member every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support pin configuration in sparse pin spaceMasahiro Yamada2016-05-311-44/+42
| | | | | | | | | | Unfortunately, the pin number of the new SoC, PH1-LD11, is not contiguous. The base frame work must be adjusted to support the new SoC pinctrl driver. The pin_desc_get() exploits radix-tree for pin look-up, so it works more efficiently with sparse pin space. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: support 3-bit drive strength controlMasahiro Yamada2016-05-312-6/+21
| | | | | | | | | The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Drive strength of some pins are controlled by 3-bit width registers (8-level granularity). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rename macros for drive strength controlMasahiro Yamada2016-05-318-1407/+1407
| | | | | | | | | | | | | | | | | | | | | The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Some of the configuration registers on it have 3-bit width. The feature will be supported in the next commit, but a problem is that macro names are getting longer and longer in the current naming scheme. Before moving forward, this commit renames macros as follows: UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4 UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5 UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: allocate struct pinctrl_desc in probe functionMasahiro Yamada2016-05-318-54/+33
| | | | | | | | | | | | Currently, every SoC driver defines struct pinctrl_desc statically, i.e. it consumes memory footprint even if it is not probed. In multi-platform, many pinctrl drivers are linked (generally as built-in objects), although only one of them is actually used. So, it is reasonable to allocate memory dynamically where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: set pinctrl_desc name in common probe functionMasahiro Yamada2016-05-317-24/+7
| | | | | | | | | Every SoC driver sets the same name for struct pinctrl_desc and platform_driver. The common probe function can set desc->name instead of duplicating strings in each SoC driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: set pinctrl_desc owner in common probe functionMasahiro Yamada2016-05-317-6/+1
| | | | | | | | The owner of the struct pinctrl_desc matches that of platform_driver. Set it in the common probe function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix register offsets for drive strength controlMasahiro Yamada2016-05-315-46/+46
| | | | | | | | These pin tables were generated by parsing hardware documents with a script, but the script had a bug. Fix the register offsets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rename function and variable namesMasahiro Yamada2016-05-316-126/+126
| | | | | | | Make function/variable names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix .pin_dbg_show() callbackMasahiro Yamada2016-05-311-0/+6
| | | | | | | | Without this, reading the "pins" in the debugfs causes kernel BUG. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: Use devm_pinctrl_register() for pinctrl registrationLaxman Dewangan2016-04-218-19/+1
| | | | | | | | | | Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_mapIrina Tirdea2016-04-011-1/+1
| | | | | | | | | | | Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rename CONFIG options and file namesMasahiro Yamada2016-03-098-13/+13
| | | | | | | | | The current "CONFIG_PINCTRL_UNIPHIER_PH1_*" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: add COMPILE_TEST optionMasahiro Yamada2016-02-101-1/+1
| | | | | | | Add COMPILE_TEST for the compilation test coverage. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: rework UniPhier pinctrl entries in KconfigMasahiro Yamada2015-12-011-10/+13
| | | | | | | | | There is a plan to support more pinctrl drivers for this SoC family. Move the driver entries into a sub menu by using "menuconfig". Also, add the missing dependency "depends on OF && MFD_SYSCON". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.4-1' of ↵Linus Torvalds2015-11-029-11/+51
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the big bulk of pin control changes for the v4.4 kernel development cycle. Development pace is high in pin control again this merge window. 28 contributors, 83 patches. It hits a few sites outside the pin control subsystem: - Device tree bindings in Documentation (as usual) - MAINTAINERS - drivers/base/* for the "init" state handling by Doug Anderson. This has been ACKed by Greg. - drivers/usb/renesas_usbhs/rcar2.c, for a dependent Renesas change in the USB subsystem. This has been ACKed by both Greg and Felipe. - arch/arm/boot/dts/sama5d2.dtsi - this should ideally have gone through the ARM SoC tree but ended up here. This time I am using Geert Uytterhoeven as submaintainer for SH PFC since the are three-four people working in parallel with new Renesas ASICs. Summary of changes: Infrastructure: - Doug Anderson wrote a patch adding an "init" state different from the "default" state for pin control state handling in the core framework. This is applied before the driver's probe() call if defined and takes precedence over "default". If both are defined, "init" will be applied *before* probe() and "default" will be applied *after* probe(). Significant subdriver improvements: - SH PFC is switched to getting GPIO ranges from the device tree ranges property on DT platforms. - Got rid of CONFIG_ARCH_SHMOBILE_LEGACY, we are all modernized. - Got rid of SH PFC hardcoded IRQ numbers. - Allwinner sunxi external interrupt through the "r" controller. - Moved the Cygnus driver to use DT-provided GPIO ranges. New drivers: - Atmel PIO4 pin controller for the SAMA4D2 family New subdrivers: - Rockchip RK3036 subdriver - Renesas SH PFC R8A7795 subdriver - Allwinner sunxi A83T PIO subdriver - Freescale i.MX7d iomux lpsr subdriver - Marvell Berlin BG4CT subdriver - SiRF Atlas 7 step B SoC subdriver - Intel Broxton SoC subdriver Apart from this, the usual slew if syntactic and semantic fixes" * tag 'pinctrl-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (81 commits) pinctrl: pinconf: remove needless loop pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER pinctrl: zynq: fix UTF-8 errors pinctrl: zynq: Initialize early pinctrl: at91: add missing of_node_put pinctrl: tegra-xusb: Correct lane mux options pinctrl: intel: Add Intel Broxton pin controller support pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt drivers/pinctrl: Add the concept of an "init" state pinctrl: uniphier: set input-enable before pin-muxing pinctrl: cygnus: Add new compatible string for gpio controller driver pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driver pinctrl: cygnus: Optional DT property to support pin mappings pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontroller pinctrl: sunxi: Fix irq_of_xlate for the r_pio pinctrl block pinctrl: sh-pfc: Remove obsolete r8a7778 platform_device_id entry pinctrl: sh-pfc: Remove obsolete r8a7779 platform_device_id entry pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h> usb: renesas_usbhs: Remove unneeded #include <linux/platform_data/gpio-rcar.h> ...
| * pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIERMasahiro Yamada2015-10-312-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long (it would break the indentation in drivers/pinctrl/Makefile), so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: set input-enable before pin-muxingMasahiro Yamada2015-10-271-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: add SD card pinmux settingsMasahiro Yamada2015-10-026-0/+36
| | | | | | | | | | | | | | | | Add SD card pinmux settings for PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXstream2, and PH1-LD6b SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: uniphier: fix input enable settings for PH1-sLD8Masahiro Yamada2015-10-021-113/+113
|/ | | | | | | | | | | | Currently, input enable settings are missing from the PH1-sLD8 pinctrl driver. (All the entries in the pin table are set to UNIPHIER_PIN_IECTRL_NONE). Fill the table with correct values. Fixes: 95372f9dc892 ("pinctrl: UniPhier: add UniPhier PH1-sLD8 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux settingMasahiro Yamada2015-08-131-0/+5
| | | | | | | The initial version of this driver missed to add I2C ch6 pin-muxing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-07-163-0/+1279
| | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-07-163-0/+1274
| | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-07-163-0/+1351
| | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-07-163-0/+799
| | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-07-163-0/+1559
| | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-07-163-0/+892
| | | | | | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Changes in v2: - sort groups and funcs alphabetically - add missing "emmc_dat8" group - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: UniPhier: add UniPhier pinctrl core supportMasahiro Yamada2015-07-164-0/+910
The core support for the pinctrl drivers for all the UniPhier SoCs. Changes in v2: - drop vogus THIS_MODULE because this file is always built-in - drop vogus "include <linux/module.h> because this file is always built-in Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 04:00:20 +0100