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2014-01-16clk: qcom: Add support for phase locked loops (PLLs)Stephen Boyd3-0/+289
2014-01-16clk: qcom: Add a regmap type clock structStephen Boyd6-0/+170
2014-01-16clk: Add set_rate_and_parent() opStephen Boyd3-19/+77
2014-01-16reset: Silence warning in reset-controller.hStephen Boyd1-0/+1
2014-01-16clk: sirf: re-arch to make the codes support both prima2 and atlas6Barry Song7-172/+458
2014-01-15clk: composite: pass mux_hw into determine_rateMike Turquette1-1/+1
2014-01-14clk: shmobile: Fix MSTP clock array initializationValentine Barshak1-2/+6
2014-01-14clk: shmobile: Fix MSTP clock indexValentine Barshak1-2/+2
2014-01-08ARM: dts: Add clock provider specific properties to max77686 nodeTomasz Figa3-0/+3
2014-01-08clk: max77686: Register OF clock providerTomasz Figa3-0/+65
2014-01-08clk: max77686: Refactor driver data handlingTomasz Figa1-13/+14
2014-01-08clk: max77686: Fix clean-up in error and remove pathsTomasz Figa1-19/+10
2014-01-08clk: max77686: Make max77686_clk_register() return struct clk *Tomasz Figa1-7/+10
2014-01-08clk: max77686: Refactor successful exit of probe functionTomasz Figa1-2/+1
2014-01-08clk: max77686: Provide .recalc_rate() operationTomasz Figa1-0/+7
2014-01-08clk: max77686: Correct callback used for checking clock statusTomasz Figa1-2/+2
2014-01-08MAINTAINERS: Add entry for Samsung SoC clock driversTomasz Figa1-0/+6
2014-01-08ARM: dts: exynos5420: add input clocks to audss clock controllerAndrew Bresticker1-2/+2
2014-01-08clk: exynos-audss: add support for Exynos 5420Andrew Bresticker3-10/+40
2014-01-08ARM: dts: exynos5250: add input clocks to audss clock controllerAndrew Bresticker1-0/+2
2014-01-08clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker3-1/+3
2014-01-08clk: exynos-audss: allow input clocks to be specified in device treeAndrew Bresticker2-7/+50
2014-01-08clk: exynos-audss: convert to platform deviceAndrew Bresticker1-16/+88
2014-01-08clk: exynos5440: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-47/+34