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* Merge tag 'exynos-arch-2' of ↵Arnd Bergmann2013-06-201-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc From Kukjin Kim: arch/arm/mach-exynos update - enable XHCI on exynos5 - enable Pinctrl on exynos4 and exynos5 - calling scu_enable() is only available on Cortex-A9 * tag 'exynos-arch-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level ARM: EXYNOS: Enable XHCI support on exynos5 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip levelDoug Anderson2013-06-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be missing the pincontrol definitions. Move PINCTRL selects to the arch level since we should be enabling the code for all exynos variants. Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS kernel config. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * Merge tag 'renesas-fixes-for-v3.10' of ↵Olof Johansson2013-06-081-9/+36
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes From Simon Horman, Renesas ARM based SoC fixes for v3.10: - Correction to USB OVC and PENC pin groupings on r8a7779 SoC. This avoids conflicts when the USB_OVCn pins are used by another function. This has been observed to be a problem in v3.10-rc1. - Update CMT clock rating for sh73a0 SoC to resolve boot failure on kzm9g-reference. This resolves a regression between v3.9 and v3.10-rc1. * tag 'renesas-fixes-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 sh-pfc: r8a7779: Don't group USB OVC and PENC pins Signed-off-by: Olof Johansson <olof@lixom.net>
* | \ Merge tag 'u300-multiplatform' of ↵Arnd Bergmann2013-06-202-16/+26
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc From Linus Walleij: Device Tree and Multiplatform support for U300: - Add devicetree support to timer, pinctrl (probe), I2C block, watchdog, DMA controller and clocks. - Piecewise add a device tree containing all peripherals. - Delete the ATAG boot path. - Delete redundant platform data and board files. - Convert to multiplatform. * tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits) ARM: u300: switch to using syscon regmap for board ARM: u300: Update MMC configs for u300 defconfig spi: pl022: use DMA by default when probing from DT pinctrl: get rid of all platform data for coh901 ARM: u300: convert MMC/SD clock to device tree ARM: u300: move the gated system controller clocks to DT i2c: stu300: do not request a specific clock name clk: move the U300 fixed and fixed-factor to DT ARM: u300: remove register definition file ARM: u300: add syscon node ARM: u300 use module_spi_driver to register driver ARM: u300: delete remnant machine headers ARM: u300: convert to multiplatform ARM: u300: localize <mach/u300-regs.h> ARM: u300: delete <mach/irqs.h> ARM: u300: delete <mach/hardware.h> ARM: u300: push down syscon registers ARM: u300: remove deps from debug macro ARM: u300: move debugmacro to debug includes ARM: u300: delete all static board data ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | pinctrl: get rid of all platform data for coh901Linus Walleij2013-06-171-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This deletes the dependency on any platform data for the COH901 pin controller. There is only one user in the kernel, and if we at some point want to support more variants, they shall provide their variant info through the device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: coh901: add device tree supportLinus Walleij2013-05-311-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes it possible to probe the COH901 pinctrl driver from the device tree, and assigned the device tree node in the gpio_chip so we can look up cross-references from the device tree. Start grabbing the per-port (bank) IRQs by index instead of by name so we don't have to look up the IRQs by name going forward. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: u300 device tree supportLinus Walleij2013-05-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple device tree compat string for the U300 pin controller. The base address is already passed properly as a resource and everything works fine. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge branch 'clps711x/soc' into next/socOlof Johansson2013-06-128-10/+310
|\ \ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Alexander Shiyan, this is a series of cleanups of clps711x, movig it closer to multiplatform and cleans up a bunch of old code. * clps711x/soc: ARM: clps711x: Update defconfig ARM: clps711x: Add support for SYSCON driver ARM: clps711x: edb7211: Control LCD backlight via PWM ARM: clps711x: edb7211: Add support for I2C ARM: clps711x: Optimize interrupt handling ARM: clps711x: Add clocksource framework ARM: clps711x: Replace "arch_initcall" in common code with ".init_early" ARM: clps711x: Move specific definitions from hardware.h to boards files ARM: clps711x: p720t: Define PLD registers as GPIOs ARM: clps711x: autcpu12: Move remaining specific definitions to board file ARM: clps711x: autcpu12: Special driver for handling memory is removed ARM: clps711x: autcpu12: Add support for NOR flash ARM: clps711x: autcpu12: Move LCD DPOT definitions to board file ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency ARM: clps711x: Re-add GPIO support GPIO: clps711x: Add DT support GPIO: clps711x: Rewrite driver for using generic GPIO code + Linux 3.10-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | pinctrl: pinconf: take the right mutexLinus Walleij2013-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinconf_dgb_config_print() takes the per-pincontroller mutex, when what it wants to take is actually the pin maps mutex. Reported-by: James Hogan <james.hogan@imgtec.com> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sunxi: fix error return code in sunxi_pinctrl_probe()Wei Yongjun2013-05-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix to return a negative error code from the devm_clk_get() error handling case instead of 0, as done elsewhere in this function. Introduced by commit 950707c0eb5c7aeaa2c446a04c824f4be686d2f6 (pinctrl: sunxi: add clock support) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: exynos: Handle suspend/resume of GPIO EINT registersTomasz Figa2013-05-272-3/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some GPIO EINT control registers needs to be preserved across suspend/resume cycle. This patch extends the driver to take care of this. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: samsung: Allow per-bank SoC-specific private dataTomasz Figa2013-05-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends pin bank descriptor structure with SoC-specific private data field that allows SoC-specific drivers to store their own private data. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: samsung: Add support for SoC-specific suspend/resume callbacksTomasz Figa2013-05-272-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC-specific driver might require additional save and restore of registers. This patch adds pair of SoC-specific callbacks per pinctrl device to account for this. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: Don't override the error code in probe error handlingAxel Lin2013-05-273-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, we return 0 in probe error paths when gpiochip_remove() returns 0. Also show error message if gpiochip_remove() fails. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: exynos: Add support for set_irq_wake of wake-up EINTsTomasz Figa2013-05-271-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support of IRQ wake-up ability configuration for wake-up EINTs on Exynos SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: samsung: fix suspend/resume functionalityDoug Anderson2013-05-272-0/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO states need to be restored after s2r and this is not currently supported in the pinctrl driver. This patch saves the gpio states before suspend and restores them after resume. Saving and restoring is done very early using syscore_ops and must happen before pins are released from their powerdown state. Patch originally from Prathyush K <prathyush.k@samsung.com> but rewritten by Doug Anderson <dianders@chromium.org>. Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entryPhil Edworthy2013-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The list of functions selected by the MOD_SEL2 register was missing an entry. This caused all entries after this to modify the MOD_SEL2 register incorrectly. This bug showed up when selecting i2c2_c pins on the Renesas Hurricane board. This bug has been present since pinmux support was added for the r8a7779 SoC by 881023d28b465eb457067dc8bbca0f24d8b34279 ("sh-pfc: Add r8a7779 pinmux support") in v3.8-rc4. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfacesGuennadi Liakhovetski2013-06-051-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinmux groups and functions for the two MMCIF and four SDHI interfaces on r8a73a4 (APE6). Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add MMCIF pin groupsKuninori Morimoto2013-06-051-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MMCIF CLK/CMD/DATA groups to R8A7778 PFC driver. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add HSPI pin groupsKuninori Morimoto2013-06-051-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add HSPI CLK/CS/RX/TX pin groups to R8A7778 PFC driver. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add I2C pin groupsKuninori Morimoto2013-06-051-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C SDA/SCL pin groups to R8A7778 PFC driver. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | pinctrl: sh-pfc: fix a typo in pfc-r8a7790Guennadi Liakhovetski2013-06-051-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix multiple occurrences of the "RESEVED" typo. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | pinctrl: sh-pfc: fix r8a7790 Function Select register tablesGuennadi Liakhovetski2013-06-051-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix several errors in Peripheral Function Select register tables for r8a7790, which prevent various function pins from being correctly configured. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: fixup IRQ1A settingsKuninori Morimoto2013-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IP2[31] func2 is IRQ1A, not IRQ3A Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7779: add Ether pin groupsSergei Shtylyov2013-06-051-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Ether RMII/LINK/MAGIC pin groups to R8A7779 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add Ether pin groupsSergei Shtylyov2013-06-051-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Ether RMII/LINK/MAGIC pin groups to R8A7778 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add VIN pin groupsVladimir Barinov2013-06-051-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add VIN DATA[0:8]/CLK/HSYNC/VSYNC pin groups to R8A7778 PFC driver. While at it, add SH_PFC_MUX8() macro for 8-bit data busses. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> [Sergei: updated the copyrights, added SH_PFC_MUX8() macro for 8-bit data bus, made use of SH_PFC_*() macros to define the pin groups.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: sh73a0: Remove function GPIOsLaurent Pinchart2013-06-051-395/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | No sh73a0 platform use the function GPIOs API. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7790: Add TPU pin groups and functionsLaurent Pinchart2013-06-051-0/+41
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Add TPU pin groups and functionsLaurent Pinchart2013-06-051-0/+50
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: sh73a0: Add TPU pin groups and functionsLaurent Pinchart2013-06-051-0/+213
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: add USB pin groupsSergei Shtylyov2013-06-051-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB0/1 PENC/USB_OVC pin groups to R8A7778 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: sh73a0: Add VCCQ MC0 regulatorLaurent Pinchart2013-06-052-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sh73a0 has an internal power gate on the VCCQ power supply for the SDHI0 device that is controlled (for some strange reason) by a bit in a PFC register. This feature should be exposed as a regulator. As the same register is also used for pin control purposes there is no way to achieve atomic read/write sequences with a separate regulator driver. We thus need to implement the regulator here. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: Add support for SoC-specific initializationLaurent Pinchart2013-06-053-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two optional init and exit SoC operations and call them from the core at probe and remove time. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: tidyup SDHI naming suffixes and sort it alphabeticallyKuninori Morimoto2013-06-051-84/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDHI 1/2 are the target Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7778: Fix outdated GPIO_FN commentsLaurent Pinchart2013-06-051-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function GPIOs have been removed, remove comments that refer to them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Add bias (pull-up/down) pinconf supportLaurent Pinchart2013-06-051-145/+220
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Replace GPIO_PORTx enum with GPIO port numbersLaurent Pinchart2013-06-051-32/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PFC GPIO API implementation moved to using port numbers. Replace all GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx enum values are identical to the port number on this platform. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove function GPIOsLaurent Pinchart2013-06-051-205/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | No r8a7740 platform use the function GPIOs API. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove HDMI function GPIOSLaurent Pinchart2013-06-041-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the HDMI pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove FSI function GPIOSLaurent Pinchart2013-06-041-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the FSI pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove CEU function GPIOSLaurent Pinchart2013-06-041-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the CEU pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove GETHER function GPIOSLaurent Pinchart2013-06-041-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the GETHER pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove BSC function GPIOSLaurent Pinchart2013-06-041-24/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the BSC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove INTC function GPIOSLaurent Pinchart2013-06-041-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the INTC pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Remove SCIF function GPIOSLaurent Pinchart2013-06-041-72/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All r8a7740 platforms now use the pinctrl API to control the SCIF pins, the corresponding function GPIOS are unused. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Hardcode the LCDC0 outputLaurent Pinchart2013-06-041-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The r8a7740 has two LCDC units and two sets of LCDC output signals. By default LCDC0 is routed to the LCD0 signals, and LCDC1 to the LCD1 signals. However, LCDC1 can be routed to the LCD0 signals by setting bit MSEL6 in MSEL3CR (the LCD0 signals are further pinmuxed the usual way). This could be configured by duplicating the LCD0 pin groups for LCDC1. However, this would unnecessarily complicate the LCD pin groups, as no r8a7740 board supported in mainline use such a configuration. Hardcode the MSEL3CR MSEL6 bit to 0 for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Add HDMI pin groups and functionsLaurent Pinchart2013-06-041-0/+14
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Add FSI pin groups and functionsLaurent Pinchart2013-06-041-0/+118
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | sh-pfc: r8a7740: Add CEU pin groups and functionsLaurent Pinchart2013-06-041-0/+124
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-11 17:53:49 +0100