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* Merge tag 'pinctrl-v5.1-1' of ↵Linus Torvalds2019-03-1146-801/+2274
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is a calm cycle, not much happened this time around: not even much incremental development. Some three new drivers, that is all. No core changes. New drivers: - NXP (ex Freescale) i.MX 8QM driver. - NXP (ex Freescale) i.MX 8MM driver. - AT91 SAM9X60 subdriver. Improvements: - Support for external interrups (EINT) on Mediatek virtual GPIOs. - Make BCM2835 pin config fully generic. - Lots of Renesas SH-PFC incremental improvements" * tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits) pinctrl: imx: fix scu link errors dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding pinctrl: qcom: spmi-gpio: Reorder debug print pinctrl: nomadik: fix possible object reference leak pinctrl: stm32: return error upon hwspinlock failure pinctrl: stm32: fix memory leak issue pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions pinctrl: sh-pfc: Validate fixed-size field widths at build time pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group pinctrl: sh-pfc: emev2: Add missing pinmux functions pinctrl: sunxi: Support I/O bias voltage setting on A80 pinctrl: ingenic: Add LCD pins for the JZ4725B SoC pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl pinctrl: bcm2835: declare pin config as generic pinctrl: qcom: qcs404: Drop unused UFS_RESET macro dt-bindings: add documentation for slew rate ...
| * pinctrl: imx: fix scu link errorsAnders Roxell2019-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PINCTRL_IMX8QM and PINCTRL_IMX8QXP will select PINCTRL_IMX_SCU. However, PINCTRL_IMX_SCU may not be valid due to it depends on IMX_MBOX. Then we may meet the following link errors: ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinctrl_sc_ipc_init': pinctrl-scu.c:(.text+0x10): undefined reference to `imx_scu_get_handle' ld: pinctrl-scu.c:(.text+0x10): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_get_handle' ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_get_scu': pinctrl-scu.c:(.text+0xa0): undefined reference to `imx_scu_call_rpc' ld: pinctrl-scu.c:(.text+0xa0): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_set_scu': pinctrl-scu.c:(.text+0x1b4): undefined reference to `imx_scu_call_rpc' ld: pinctrl-scu.c:(.text+0x1b4): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' ld: drivers/pinctrl/freescale/pinctrl-imx8qxp.o: in function `imx8qxp_pinctrl_probe': pinctrl-imx8qxp.c:(.text+0x28): undefined reference to `imx_pinctrl_probe' ld: pinctrl-imx8qxp.c:(.text+0x28): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_pinctrl_probe' Rework so that PINCTRL_IMX8QM and PINCTRL_IMX8QXP depends on IMX_SCU as well in case they're wrongly enabled. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Reorder debug printBjorn Andersson2019-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's reasonable to expect that people turn to the "gpio" debugfs file to first and foremost learn about the direction and value of a gpio, and second to that about it's pinconf. So reorder the value so each line reads: gpioN: direction value ... This also makes it consistent with the TLMM pinctrl driver's output in the same dump. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: fix possible object reference leakWangBo2019-02-201-4/+13
| | | | | | | | | | | | | | | | The of_find_device_by_node takes a reference to the struct device when find the match device ,we should release it when fail. Signed-off-by: WangBo <wang.bo116@zte.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: return error upon hwspinlock failureAlexandre Torgue2019-02-201-20/+24
| | | | | | | | | | | | | | Return error to the caller when the hwspinlock can't get locked. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: fix memory leak issueAlexandre Torgue2019-02-201-10/+16
| | | | | | | | | | | | | | | | | | configs is allocated by pinconf_generic_parse_dt_config(), pinctrl_utils_add_map_configs() duplicates configs so it can and has to be freed to prevent memory leaks. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v5.1-tag2' of ↵Linus Walleij2019-02-137-5/+677
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.1 (take two) - Add DRIF (digital radio) pin groups on R-Car E3 and M3-N, - Add TMU (timer) pin groups on R-Car M3-N, - Miscellaneous fixes, - Build-time validation for fixed-size field width mismatches.
| | * pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functionsTakeshi Kihara2019-02-111-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Based on a similar patch of the R8A7796 PFC driver by Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functionsTakeshi Kihara2019-02-111-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Validate fixed-size field widths at build timeGeert Uytterhoeven2019-02-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a build-time check, to ensure the register and field widths in descriptors for config registers with fixed-width fields are sane. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groupsGeert Uytterhoeven2019-02-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are two pin groups for the FSIC SPDIF signal, but the FSIC pin group array lists only one, and it refers to a nonexistent group. Fixes: 2ecd4154c906b7d6 ("sh-pfc: sh73a0: Add FSI pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin groupGeert Uytterhoeven2019-02-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The vin1_data18_b pin group itself is present, but it is not listed in the VIN1 pin group array, and thus cannot be selected. Fixes: 7dd74bb1f058786e ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin groupGeert Uytterhoeven2019-02-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The entry for "scifb2_data_c" in the SCIFB2 pin group array contains a typo, thus the group cannot be selected. Fixes: 5088451962389924 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: emev2: Add missing pinmux functionsGeert Uytterhoeven2019-02-111-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The err_rst_reqb, ext_clki, lowpwr, and ref_clko pin groups are present, but no pinmux functions refer to them, hence they can not be selected. Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functionsTakeshi Kihara2019-02-051-2/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sunxi: Support I/O bias voltage setting on A80Chen-Yu Tsai2019-02-114-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A80 SoC has configuration registers for I/O bias voltage. Incorrect settings would make the affected peripherals inoperable in some cases, such as Ethernet RGMII signals biased at 2.5V with the settings still at 3.3V. However low speed signals such as MDIO on the same group of pins seem to be unaffected. Previously there was no way to know what the actual voltage used was, short of hard-coding a value in the device tree. With the new pin bank regulator supply support in place, the driver can now query the regulator for its voltage, and if it's valid (as opposed to being the dummy regulator), set the bias voltage setting accordingly. Add a quirk to denote the presence of the configuration registers, and a function to set the correct setting based on the voltage read back from the regulator. This is only done when the regulator is first acquired and enabled. While it would be nice to have a notifier on the regulator so that when the voltage changes, the driver can update the setting, in practice no board currently supports dynamic changing of the I/O voltages. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'v5.0-rc6' into develLinus Walleij2019-02-116-29/+37
| |\ \ | | | | | | | | | | | | Linux 5.0-rc6
| * | | pinctrl: ingenic: Add LCD pins for the JZ4725B SoCPaul Cercueil2019-02-081-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pins and groups for the "lcd" pin function in the JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: samsung: Remove legacy API for handling external wakeup interrupts maskKrzysztof Kozlowski2019-02-081-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the legacy, ugly API of exposing the static value of external wakeup interrupts mask, because all arch-machine users where converted to use generic implementation from pinctrl driver. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: bcm2835: Direct GPIO config changes to generic pinctrlStefan Wahren2019-02-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support GPIO config changes direct these to the generic pinctrl. This also requires an adjust of the return code for unsupported parameter otherwise gpiod_configure_flags wont work as expected. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: bcm2835: declare pin config as genericStefan Wahren2019-02-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0de704955ee44 ("pinctrl: bcm2835: Add support for generic pinctrl binding") this driver is capable to use the generic interface. So declare this accordingly. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: qcom: qcs404: Drop unused UFS_RESET macroBjorn Andersson2019-02-081-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The UFS_RESET macro serves no purpose on QCS404, remove it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: add slewrate support for SAM9X60Claudiu Beznea2019-02-082-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add slew rate support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: add compatibles for SAM9X60 pin controllerClaudiu Beznea2019-02-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatibles for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: add drive strength support for SAM9X60Claudiu Beznea2019-02-082-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add drive strength support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: add option to use drive strength bitsClaudiu Beznea2019-02-081-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAM9X60 uses high and low drive strengths. To implement this, in at91_pinctrl_mux_ops::set_drivestrength and at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of drive strengths (1 for low, 2 for high), thus change the code to allow the usage of drive strength bit numbers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: freescale: Add imx8mm pinctrl driver supportBai Ping2019-01-303-0/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pinctrl driver support for i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".Zhou Yanjie2019-01-301-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original code, some function names begin with "ingenic_gpio_", and some with "gpio_ingenic_". For the sake of uniform style, all of them are changed to the beginning of "ingenic_gpio_". Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.Zhou Yanjie2019-01-301-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mmc2 for JZ4770 and JZ4780: According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this part of the original code is missing. It is worth noting that JZ4770's mmc2 supports 8bit mode while JZ4780's does not, so we added the corresponding code for both models. Add nemc-wait for JZ4770 and JZ4780: Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the original code is missing. Add mac for JZ4770: JZ4770 have a mac. But this part of the original code is missing. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.Zhou Yanjie2019-01-301-58/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete uart4 and i2c3/4 from JZ4770: According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we remove it from the JZ4770 code and add a section corresponding the JZ4780. Fix bugs in i2c0/1: The pin number was wrong in the original code. Fix bugs in uart2: JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc0: JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc1: JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in nemc: JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. And add missing cs2~5 groups for JZ4770 and JZ4780. Fix bugs in cim: JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in lcd: Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: berlin: as370: use generic "pwm" as pwm function nameJisheng Zhang2019-01-281-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we could use the generic "pwm" for two or more pins, e.g pwm0_pmux: pwm0-pmux { groups = "PWM0", "PWM1"; function = "pwm"; }; Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'sh-pfc-for-v5.1-tag1' of ↵Linus Walleij2019-01-2812-343/+288
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.1 - Add TMU pin groups on R-Car E3, - Miscellaneous fixes and cleanups.
| | * | pinctrl: sh-pfc: r8a7778: Fix HSPI pin numbers and namesGeert Uytterhoeven2019-01-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When declaring the HSPI RX1_B and TX1_B pins, two mistakes were made: - the rows and columns in the BGA pin matrix, from which the pin numbers are derived, were exchanged, - it was not taken into account that pin row labelling skips characters I, O, Q, and S. Fix the order, and the corresponding pin names. Notes: - The actual values of the pin numbers don't really matter (they just have to be unique), so the wrong order didn't have any impact, - Changing the names of the pins is user-visible, but there are no users in (upstream) DTS files. Fixes: 4f82e3ee724f1712 ("sh-pfc: Support pins not associated with a GPIO port") Fixes: 09cc76a95802e87d ("sh-pfc: r8a7778: add HSPI pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functionsTakeshi Kihara2019-01-211-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3Geert Uytterhoeven2019-01-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike R-Car M3-W, R-Car M3-N does not have DU_DOTCLKIN2, but the corresponding pin carries the DU_DOTCLKIN3 signal. Correct all references to DU_DOTCLKIN2 to fix this. This change does not have any runtime effect, as it only changes an internal enum name, and a comment. Fixes: 490e687eb8b274b5 ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groupsGeert Uytterhoeven2019-01-211-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The naming of the "b" versions of the VIN1 pin groups is a bit odd, in that the "_b" appears in the middle of the names, instead of as a suffix. Increase consistency with other SoCs by making R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N, use the recently added optional "version" argument of the VIN_DATA_PIN_GROUP() macro. Note that this breaks backwards compatibility with existing DTBs, but there are no upstream users of the "vin1_b_*" names. Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77980: Deduplicate VIN1 pin definitionsGeert Uytterhoeven2019-01-211-43/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data12 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN1 channel. This reduces kernel size by 144 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitionsGeert Uytterhoeven2019-01-211-86/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data12 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN0 and VIN1 channels. This reduces kernel size by 288 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitionsGeert Uytterhoeven2019-01-211-64/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN5 channel. This reduces kernel size by 240 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitionsGeert Uytterhoeven2019-01-211-64/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN5 channel. This reduces kernel size by 240 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7794: Initialize TDSEL register for ES1.0Wolfram Sang2019-01-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation for ES1.0 says that some bits in TDSEL must be set (ch 5.3.35 in R-Car E2 v0.5). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions and use whitelisting for ES versions known to need this. This is needed for some SD cards supporting SDR104 transfer mode. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7790: Initialize TDSEL register for ES1.0Wolfram Sang2019-01-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation for ES1.0 says that some bits in TDSEL must be set (ch 5.3.39 in R-Car H2 v0.91). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions and use whitelisting for ES versions known to need this. This is needed for some SD cards supporting SDR104 transfer mode. For me, TDSEL was not initialized by the firmware and I had problems with the card when re-inserting it. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: Print pin group when debuggingGeert Uytterhoeven2019-01-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Knowing which pin group is being configured is useful information when debugging pin configuration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"Geert Uytterhoeven2019-01-211-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit f4caa6ee736fa8a46c806ba4382c16f7e5a20248. The same can be expressed better by dropping the SH_PFC_PIN_CFG_PULL_DOWN flag from the GPIO description, as it includes returning an error to the caller when trying to configure the pin for pull-down, causing: sh-pfc e6060000.pin-controller: pin_config_set op failed for pin 201 sh-pfc e6060000.pin-controller: Error applying setting, reverse things back sh-pfc e6060000.pin-controller: failed to select default state Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capabilityGeert Uytterhoeven2019-01-211-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flag from the GP6_9 GPIO description. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numberingTakeshi Kihara2019-01-211-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOD_SEL register bit numbering was different from R-Car D3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") [shimoda: split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use a macro to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numberingTakeshi Kihara2019-01-211-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOD_SEL register bit numbering was different from R-Car E3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") [shimoda: Split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use macros to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
| | * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2Takeshi Kihara2019-01-211-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0Takeshi Kihara2019-01-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | | pinctrl: sirf: drop pointless static qualifier in sirfsoc_gpio_probeYueHaibing2019-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to have the 'sgpio' variable static since new value always be assigned before use it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 01:43:47 +0100