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* pinctrl: sunxi: Correct number of IRQ banks on H6 main pin controllerChen-Yu Tsai2019-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H6 main pin controller has four banks of interrupt-triggering pins. The driver as originally submitted only specified three, but had pin descriptions referencing a fourth bank. This results in a out-of-bounds access into .irq_array of struct sunxi_pinctrl. This however did not result in a crash until v4.20, with commit a66d972465d1 ("devres: Align data[] to ARCH_KMALLOC_MINALIGN"), which changed the alignment of memory region returned by devm_kcalloc(). The increase likely moved the out-of-bounds access into the next, unmapped page. With KASAN on, the bug is quite clear: BUG: KASAN: slab-out-of-bounds in sunxi_pinctrl_init_with_variant+0x49c/0x12b8 Write of size 4 at addr ffff80002c680280 by task swapper/0/1 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc1-00016-gc480a5e6a077 #3 Hardware name: OrangePi Lite2 (DT) Call trace: dump_backtrace+0x0/0x220 show_stack+0x14/0x20 dump_stack+0xac/0xd4 print_address_description+0x60/0x25c kasan_report+0x14c/0x1ac __asan_store4+0x80/0xa0 sunxi_pinctrl_init_with_variant+0x49c/0x12b8 h6_pinctrl_probe+0x18/0x20 platform_drv_probe+0x6c/0xc8 really_probe+0x244/0x4b0 driver_probe_device.part.4+0x11c/0x164 __driver_attach+0x120/0x190 bus_for_each_dev+0xe8/0x158 driver_attach+0x30/0x40 bus_add_driver+0x308/0x318 driver_register+0xbc/0x1d0 __platform_driver_register+0x7c/0x88 h6_pinctrl_driver_init+0x18/0x20 do_one_initcall+0xd4/0x208 kernel_init_freeable+0x230/0x2c8 kernel_init+0x10/0x108 ret_from_fork+0x10/0x1c Allocated by task 1: kasan_kmalloc.part.0+0x4c/0x100 kasan_kmalloc+0xc4/0xe8 kasan_slab_alloc+0x14/0x20 __kmalloc_track_caller+0x130/0x238 devm_kmalloc+0x34/0xd0 sunxi_pinctrl_init_with_variant+0x1d8/0x12b8 h6_pinctrl_probe+0x18/0x20 platform_drv_probe+0x6c/0xc8 really_probe+0x244/0x4b0 driver_probe_device.part.4+0x11c/0x164 __driver_attach+0x120/0x190 bus_for_each_dev+0xe8/0x158 driver_attach+0x30/0x40 bus_add_driver+0x308/0x318 driver_register+0xbc/0x1d0 __platform_driver_register+0x7c/0x88 h6_pinctrl_driver_init+0x18/0x20 do_one_initcall+0xd4/0x208 kernel_init_freeable+0x230/0x2c8 kernel_init+0x10/0x108 ret_from_fork+0x10/0x1c Freed by task 0: (stack is not available) The buggy address belongs to the object at ffff80002c680080 which belongs to the cache kmalloc-512 of size 512 The buggy address is located 0 bytes to the right of 512-byte region [ffff80002c680080, ffff80002c680280) The buggy address belongs to the page: page:ffff7e0000b1a000 count:1 mapcount:0 mapping:ffff80002e00c780 index:0xffff80002c683c80 compound_mapcount: 0 flags: 0x10200(slab|head) raw: 0000000000010200 ffff80002e003a10 ffff80002e003a10 ffff80002e00c780 raw: ffff80002c683c80 0000000000100001 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff80002c680180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffff80002c680200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffff80002c680280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ^ ffff80002c680300: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffff80002c680380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc Correct the number of IRQ banks so there are no more mismatches. Fixes: c8a830904991 ("pinctrl: sunxi: add support for the Allwinner H6 main pin controller") Cc: <stable@vger.kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mcp23s08: spi: Fix regmap allocation for mcp23s18Jason Kridner2019-01-211-1/+6
| | | | | | | | | | | | | | Fixes issue created by 9b3e4207661e67f04c72af15e29f74cd944f5964. It wasn't possible for one_regmap_config to be non-NULL at the point it was tested for mcp23s18 devices. Applied the same pattern of allocating one_regmap_config using devm_kmemdump() and then initializing the local regmap structure from that. Signed-off-by: Jason Kridner <jdk@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: cherryview: fix Strago DMI workaroundDmitry Torokhov2019-01-211-4/+4
| | | | | | | | | | | | | | | Well, hopefully 3rd time is a charm. We tried making that check DMI_BIOS_VERSION and DMI_BOARD_VERSION, but the real one is DMI_PRODUCT_VERSION. Fixes: 86c5dd6860a6 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197953 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1631930 Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Consider pin_base when calculating regulator array indexChen-Yu Tsai2019-01-142-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen), while R_PIO covers PL to PN. The regulator array only has space for 12 entries, which was designed to cover PA to PL. On the A80, the pin banks go up to PN, which would be the 14th entry in the regulator array. However since the driver only needs to track regulators for its own pin banks, the array only needs to have 9 entries, and also take in to account the value of pin_base, such that the regulator for the first pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry of the array. Base the regulator array index on pin_base, such that "PA" for PIO and "PL" for R_PIO both take the first element within their respective device's regulator array. Also decrease the size of the regulator array to 9, just enough to cover "PA" to "PI". Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Fix and simplify pin bank regulator handlingChen-Yu Tsai2019-01-141-20/+16
| | | | | | | | | | | | | | | | | The new per-pin-bank regulator handling code in the sunxi pinctrl driver has mismatched conditions for enabling and disabling the regulator: it is enabled each time a pin is requested, but only disabled when the pin-bank's reference count reaches zero. Since we are doing reference counting already, there's no need to enable the regulator each time a pin is requested. Instead we can just do it for the first requested pin of each pin-bank. Thus we can reverse the test and bail out early if it's not the first occurrence. Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators") Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: fix Kconfig build errors for moore coreRyder Lee2019-01-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | on i386 or x86_64: Lots of build errors for drivers/pinctrl/mediatek/pinctrl-moore.c when CONFIG_OF is not enabled (but COMPILE_TEST is). first this: WARNING: unmet direct dependencies detected for PINCTRL_MTK_MOORE Depends on [n]: PINCTRL [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && OF [=n] Selected by [y]: - PINCTRL_MT7623 [=y] && PINCTRL [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && (MACH_MT7623 || COMPILE_TEST [=y]) and then: ../drivers/pinctrl/mediatek/pinctrl-moore.c:22:44: error: array type has incomplete element type static const struct pinconf_generic_params mtk_custom_bindings[] = { (etc) Fixes: b5af33df50e9 ("pinctrl: mediatek: improve Kconfig dependencies") Cc: stable@vger.kernel.org Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.21-1' of ↵Linus Torvalds2019-01-01100-1099/+10585
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have no core changes but lots of incremental development in drivers all over the place: Renesas, NXP, Mediatek and Actions Semiconductor keep churning out new SoCs. I have some subtree maintainers for Renesas and Intel helping out to keep down the load, it's been working smoothly (Samsung also have a subtree but it was not used this cycle.) New drivers: - NXP (ex Freescale) i.MX 8 QXP SoC driver. - Mediatek MT6797 SoC driver. - Mediatek MT7629 SoC driver. - Actions Semiconductor S700 SoC driver. - Renesas RZ/A2 SoC driver. - Allwinner sunxi suniv F1C100 SoC driver. - Qualcomm PMS405 PMIC driver. - Microsemi Ocelot Jaguar2 SoC driver. Improvements: - Some RT improvements (using raw spinlocks where appropriate). - A lot of new pin sets on the Renesas PFC pin controllers. - GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO chips, and Xway. - Major modernization of the Intel pin control drivers. - STM32 pin control driver will now synchronize usage of pins with another CPU using a hardware spinlock" * tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits) dt-bindings: arm: fsl-scu: add imx8qm pinctrl support pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ pinctrl: imx-scu: Depend on IMX_SCU pinctrl: ocelot: Add dependency on HAS_IOMEM pinctrl: ocelot: add MSCC Jaguar2 support pinctrl: bcm: ns: support updated DT binding as syscon subnode dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon MAINTAINERS: merge at91 pinctrl entries pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP pinctrl: uniphier: constify uniphier_pinctrl_socdata pinctrl: mediatek: improve Kconfig dependencies pinctrl: msm: mark PM functions as __maybe_unused dt-bindings: pinctrl: sunxi: Add supply properties pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs" pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs" pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length ...
| * pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQAbel Vesa2018-12-271-1/+1
| | | | | | | | | | | | | | | | | | | | The CONFIG_SOC_IMX8MQ will go away, so the dependency can be based on ARCH_MXC && ARM64. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx-scu: Depend on IMX_SCUGuido Günther2018-12-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise building fails with only PINCTRL_IMX_SCU selected: aarch64-linux-gnu-ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinctrl_sc_ipc_init': pinctrl-scu.c:(.text+0x10): undefined reference to `imx_scu_get_handle' aarch64-linux-gnu-ld: pinctrl-scu.c:(.text+0x10): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_get_handle' aarch64-linux-gnu-ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_get_scu': pinctrl-scu.c:(.text+0x64): undefined reference to `imx_scu_call_rpc' aarch64-linux-gnu-ld: pinctrl-scu.c:(.text+0x64): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' aarch64-linux-gnu-ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_set_scu': pinctrl-scu.c:(.text+0x104): undefined reference to `imx_scu_call_rpc' aarch64-linux-gnu-ld: pinctrl-scu.c:(.text+0x104): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' make: *** [Makefile:1038: vmlinux] Error 1 Signed-off-by: Guido Günther <agx@sigxcpu.or> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ocelot: Add dependency on HAS_IOMEMLinus Walleij2018-12-221-0/+1
| | | | | | | | | | | | | | | | As usual the build fails on UM Linux because that thing does not have IOMEM. Depend on HAS_IOMEM solves the build problem. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v4.21-tag3' of ↵Linus Walleij2018-12-2114-36/+58
| |\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Fixes for v4.21 - Miscellaneous fixes, - Build-time validation for pins/marks mismatches.
| | * pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-lengthGeert Uytterhoeven2018-12-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pinmux_cfg_reg.var_field_width[] is actually a variable-length array, terminated by a zero, and counting at most r_width entries. Usually the number of entries is much smaller than r_width, so the ability to catch bugs at compile time through an "excess elements in array initializer" warning is fairly limited. Hence make the array variable-length, decreasing kernel size slightly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: Print actual field width for variable-width fieldsGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debug code in sh_pfc_write_config_reg() prints the width of the field being modified. However, registers with a variable-width field layout are identified by pinmux_cfg_reg.field_width being zero, hence zeroes are printed instead of the actual field widths. Fix this by printing the Hamming weight of the field mask instead, which is correct for both fixed-width and variable-width fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh7734: Fix shifted values in IPSR10Geert Uytterhoeven2018-12-181-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some values in the Peripheral Function Select Register 10 descriptor are shifted by one position, which may cause a peripheral function to be programmed incorrectly. Fixing this makes all HSCIF0 pins use Function 4 (value 3), like was already the case for the HSCK0 pin in field IP10[5:3]. Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh7734: Remove bogus IPSR10 valueGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IP10[5:3] field in Peripheral Function Select Register 10 has a width of 3 bits, i.e. it allows programming one out of 8 different configurations. However, 9 values are provided instead of 8, overflowing into the subsequent field in the register, and thus breaking the configuration of the latter. Fix this by dropping a bogus zero value. Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh7269: Add missing PCIOR0 fieldGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Port C I/O Register 0 contains 7 reserved bits, but the descriptor contains only dummy configuration values for 6 reserved bits, thus breaking the configuration of all subsequent fields in the register. Fix this by adding the two missing configuration values. Fixes: f5e811f2a43117b2 ("sh-pfc: Add sh7269 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh7264: Fix PFCR3 and PFCR0 register configurationGeert Uytterhoeven2018-12-181-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Port F Control Register 3 (PFCR3) contains only a single field. However, counting from left to right, it is the fourth field, not the first field. Insert the missing dummy configuration values (3 fields of 16 values) to fix this. The descriptor for the Port F Control Register 0 (PFCR0) lacks the description for the 4th field (PF0 Mode, PF0MD[2:0]). Add the missing configuration values to fix this. Fixes: a8d42fc4217b1ea1 ("sh-pfc: Add sh7264 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77995: Remove bogus SEL_PWM[0-3]_3 configurationsGeert Uytterhoeven2018-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the SEL_PWM[0-3] fields in the Module Select Register 0 support 4 possible configurations per PWM pin, only the first 3 are valid. Replace the invalid and unused configurations for SEL_PWM[0-3]_3 by dummies. Fixes: 794a6711764658a1 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 SEL_I2C1 field widthGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SEL_I2C1 (MOD_SEL0[21:20]) field in Module Select Register 0 has a width of 2 bits, i.e. it allows programming one out of 4 different configurations. However, the MOD_SEL0_21_20 macro contains 8 values instead of 4, overflowing into the subsequent fields in the register, and thus breaking the configuration of the latter. Fix this by dropping the bogus last 4 values, including the non-existent SEL_I2C1_4 configuration. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh7734: Add missing IPSR11 fieldGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Peripheral Function Select Register 11 contains 3 reserved bits and 15 variable-width fields, but the variable field descriptor does not contain the 3-bit field IP11[25:23]. Fixes: 856cb4bb337ee504 ("sh: Add support pinmux for SH7734") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77980: Add missing MOD_SEL0 fieldGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Module Select Register 0 contains 20 (= 5 x 4) reserved bits, and 12 single-bit fields, but the variable field descriptor lacks a field of 4 reserved bits. Fixes: f59125248a691dfe ("pinctrl: sh-pfc: Add R8A77980 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77970: Add missing MOD_SEL0 fieldGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Module Select Register 0 contains 20 (= 5 x 4) reserved bits, and 12 single-bit fields, but the variable field descriptor lacks a field of 4 reserved bits. Fixes: b92ac66a1819602b ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7794: Remove bogus IPSR9 fieldGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Peripheral Function Select Register 9 contains 12 fields, but the variable field descriptor contains a 13th bogus field of 3 bits. Fixes: 43c4436e2f1890a7 ("pinctrl: sh-pfc: add R8A7794 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: Validate pins/marks in pin groups at build timeGeert Uytterhoeven2018-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add a build-time check, to ensure the number of pins and pin marks in a pin group matches. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 groupGeert Uytterhoeven2018-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tpu4_to3_mux[] array contains the TPU4TO3 pin mark, but the tpu4_to3_pins[] array lacks the corresponding pin number. Add the missing pin number, for non-GPIO pin F26. Fixes: 5da4eb049de803c7 ("sh-pfc: sh73a0: Add TPU pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 groupGeert Uytterhoeven2018-12-181-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of the color components. The vin1_b_data18_pins[] array rightfully does not include the corresponding pin numbers, as RGB18 is subset of RGB24, containing only the 6 MSB bits of each component. Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b groupGeert Uytterhoeven2018-12-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qspi_data4_b_mux[] array contains pin marks for the clock and chip select pins. The qspi_data4_b_pins[] array rightfully does not contain the corresponding pin numbers, as the control pins are provided by a separate group (qspi_ctrl_b). Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 groupGeert Uytterhoeven2018-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers, but the lcd0_data24_1_mux[] array lacks the corresponding pin marks. Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii groupGeert Uytterhoeven2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The gether_gmii_mux[] array contains the REF125CK pin mark, but the gether_gmii_pins[] array lacks the corresponding pin number. Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3Geert Uytterhoeven2018-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3. Hence on R-Car E3, SDHI voltage state is lost after system resume. Fix this by registering the I/O Control Registers on R-Car E3, too. Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * pinctrl: rza1: Handle devm_kasprintf() failure casesNicholas Mc Guire2018-12-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_kasprintf() may return NULL on failure of internal allocation thus the assignments are not safe if not checked. On error rza1_pinctrl_register() respectively rza1_parse_gpiochip() return negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 5a49b644b307 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a77990: Add support for pull-up only pinsGeert Uytterhoeven2018-12-181-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states that the USB30_OVC pin supports pull-up only. It has a bit assigned in the pull-enable register (PUEN5), but not in the pull-up/down control register (PUD5). Add a check for this, to prevent configuring a prohibited setting. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: ocelot: add MSCC Jaguar2 supportAlexandre Belloni2018-12-212-63/+280
| | | | | | | | | | | | | | | | | | | | | | | | Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning that there are 2 registers instead of one. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: ns: support updated DT binding as syscon subnodeRafał Miłecki2018-12-211-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation has been recently updated specifying that pinctrl should be subnode of the CRU "syscon". Support that by using parent node for regmap and reading "offset" property from the DT. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: imx8qxp: break the dependency on SOC_IMX8QXPAisheng Dong2018-12-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM64 SoC does not encourage people to add more finegrained SoC config options rather than a single ARCH_<family> in arch Kconfig. So this patch aims to break the dependency on SOC_IMX8QXP. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: uniphier: constify uniphier_pinctrl_socdataMasahiro Yamada2018-12-2111-12/+12
| | | | | | | | | | | | | | | | | | | | | These are constant data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: improve Kconfig dependenciesRyder Lee2018-12-211-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove prompts to make all pinctrl cores to non-visible symbols and make sure the target SoCs would be coupled with the corresponding cores. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com Acked-by: Sean Wang <sean.wang@kernel.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: msm: mark PM functions as __maybe_unusedArnd Bergmann2018-12-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without CONFIG_PM_SLEEP, we get annoying warnings about unused functions: drivers/pinctrl/qcom/pinctrl-msm.c:1082:12: error: 'msm_pinctrl_resume' defined but not used [-Werror=unused-function] static int msm_pinctrl_resume(struct device *dev) ^~~~~~~~~~~~~~~~~~ drivers/pinctrl/qcom/pinctrl-msm.c:1075:12: error: 'msm_pinctrl_suspend' defined but not used [-Werror=unused-function] static int msm_pinctrl_suspend(struct device *dev) Mark them as __maybe_unused to shut up the warning and silently drop the functions without having to add ugly #ifdefs. Fixes: 977d057ad346 ("pinctrl: msm: Add sleep pinctrl state transitions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARDMartin Blumenstingl2018-12-211-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be configured in devicetree using groups = BOOTx or groups = CARDx. This makes the behavior consistent with other pins inside the same driver as well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers. Fixes: 0fefcb6876d0d6 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARDMartin Blumenstingl2018-12-211-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be configured in devicetree using groups = BOOTx or groups = CARDx. This makes the behavior consistent with other pins inside the same driver as well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers. Fixes: 6ac730951104a4 ("pinctrl: add driver for Amlogic Meson SoCs") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"Martin Blumenstingl2018-12-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the existing "gpio" function to "gpio_periphs". This makes it consistent with the "gpio_aobus" function. Also GXBB and GXL are also using the "gpio_periphs" naming, so this makes the code here consistent with other Amlogic pinctrl drivers. No functional changes since thee "gpio" function is currently not used. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"Martin Blumenstingl2018-12-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the existing "gpio" function to "gpio_periphs". This makes it consistent with the "gpio_aobus" function. Also GXBB and GXL are also using the "gpio_periphs" naming, so this makes the code here consistent with other Amlogic pinctrl drivers. No functional changes since thee "gpio" function is currently not used. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pinsMartin Blumenstingl2018-12-211-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N) only belong to the pin controller in the AO domain. With the current definition these pins cannot be referred to in .dts files as group (which is possible on GXBB and GXL for example). Add a separate "gpio_aobus" function to fix the mapping between the pin controller and the GPIO pins in the AO domain. This is similar to how the GXBB and GXL drivers implement this functionality. Fixes: 9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pinsMartin Blumenstingl2018-12-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N) only belong to the pin controller in the AO domain. With the current definition these pins cannot be referred to in .dts files as group (which is possible on GXBB and GXL for example). Add a separate "gpio_aobus" function to fix the mapping between the pin controller and the GPIO pins in the AO domain. This is similar to how the GXBB and GXL drivers implement this functionality. Fixes: 9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: xway: fix gpio-hog related boot issuesMartin Schiller2018-12-171-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on commit a86caa9ba5d7 ("pinctrl: msm: fix gpio-hog related boot issues"). It fixes the issue that the gpio ranges needs to be defined before gpiochip_add(). Therefore, we also have to swap the order of registering the pinctrl driver and registering the gpio chip. You also have to add the "gpio-ranges" property to the pinctrl device node to get it finally working. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed: Wrap -Woverride-init with cc-optionNathan Chancellor2018-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang does not support this option: warning: unknown warning option '-Woverride-init'; did you mean '-Woverride-module'? [-Wunknown-warning-option] 1 warning generated. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Deal with per-bank regulatorsMaxime Ripard2018-12-142-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner SoCs have on most of their GPIO banks a regulator input. This issue was mainly ignored so far because either the regulator was a static regulator that would be providing power anyway, or the bank was used for a feature unsupported so far (CSI). For the odd cases, enabling it in the bootloader was the preferred option. However, now that we are starting to support those features, and that we can't really rely on the bootloader for this, we need to model those regulators as such in the DT. This is slightly more complicated than what it looks like, since some regulators will be tied to the PMIC, and in order to have access to the PMIC bus, you need to mux its pins, which will need the pinctrl driver, that needs the regulator driver to be registered. And this is how you get a circular dependency. In practice however, the hardware cannot fall into this case since it would result in a completely unusable bus. In order to avoid that circular dependency, we can thus get and enable the regulators at pin_request time. We'll then need to account for the references of all the pins of a particular branch to know when to put the reference, but it works pretty nicely once implemented. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: Use of_node_name_eq for node name comparisonsRob Herring2018-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'intel-pinctrl-v4.21-1' of ↵Linus Walleij2018-12-1313-84/+46
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v4.21-1 Switch to generic ->probe() callbacks. Simplify getting .driver_data. Code formatting fixes and headers clean up. Special case is the driver for Intel Cherryview SoC, where GPIO enabling bit was mistakenly cleared when pin gets freed. It's fixed now. The below commit went to v4.20-rc3, that's why duplication. - ad774315c3765ffb27abb6db987a2121d871a942 MAINTAINERS: Add tree link for Intel pin control driver The following is an automated git shortlog grouped by driver: baytrail: - Code formatting fixes - simplify getting .driver_data broxton: - Code formatting fixes - Get rid of unneeded ->probe() stub cannonlake: - Code formatting fixes - Get rid of unneeded ->probe() stub cedarfork: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub cherryview: - Stop clearing the GPIO_EN bit from chv_gpio_disable_free - Add chv_gpio_clear_triggering() helper function - simplify getting .driver_data denverton: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub geminilake: - Code formatting fixes icelake: - Code formatting fixes - Get rid of unneeded ->probe() stub intel: - Unexport intel_pinctrl_probe() - simplify getting .driver_data lewisburg: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub MAINTAINERS: - Add tree link for Intel pin control driver merrifield: - include bits.h instead of bitops.h sunrisepoint: - Get rid of unneeded ->probe() stub
| | * | pinctrl: cherryview: Stop clearing the GPIO_EN bit from chv_gpio_disable_freeHans de Goede2018-12-051-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clearing the GPIO_EN bit from chv_gpio_disable_free is a bad idea and pinctrl-cherryview.c is the only Intel pinctrl driver doing something like this. Clearing the GPIO_EN bit means that if the pin was an output it is now effectively floating. The datasheet is not clear what happens to pull ups / downs in this case, but from testing it looks like these are disabled too, also floating input pins. One example where this is causing issues is the soc_button_array input driver, this parses ACPI tables to create 2 platform devices for the gpio_keys input driver. The list of GPIOs is passed through struct gpio_keys_platform_data which uses gpio numbers rather then gpio_desc pointers. The buttons handled by this drivers short the pin to ground when pressed and the volume buttons rely on the SoC's internal pull-up to pull the pin high when the button is not pressed. To get the gpio number, the soc_button_array code calls gpiod_get_index followed by a desc_to_gpio call and then gpiod_put on the gpio_desc. This last call causes chv_gpio_disable_free to clear the GPIO_EN bit. When the gpio_keys driver then loads next it gets the gpio_desc again causing the GPIO_EN bit to be set again and immediately reads the GPIO value which for the volume buttons reads 0 at this time, causing a spurious press of the volume buttons to get reported. Putting a small delay between the gpio_desc request and the read fixes this, I assume that this is caused by the pull-up being temporarily disabled while the GPIO_EN bit is cleared as the powerbutton which also has its GPIO_EN bit cleared does not have this problem. The soc_button_array code is not the only code temporarily requesting GPIOs the DWC3 PCI code also does this, to set the enable and reset GPIOs for the external phy, so that the code instantiating the ULPI phy can read the vendor and product ID registers from the phy. These GPIOs are released after this so that the PHY driver can claim and use them when it loads. Another example of temporary GPIO usage would be a user-space set_gpio utility using the userspace ioctls to set a GPIO as output value 0 or 1, having the GPIO revert to floating as soon as this utility exits would certainly be unexpected behavior. One argument in favor of clearing the GPIO_EN bit is if the GPIO is going to be muxed to another function after being released, but in that case chv_pinmux_set_mux() already clears it. TL;DR: Clearing the GPIO_EN bit from is a bad idea, this commit therefor removes the clearing from chv_gpio_disable_free(), replacing it with code to clear the interrupt-trigger condition so that the GPIO stops generating interrupts when released, as pinctrl-baytrail.c does. Note this commit adds a !chv_pad_locked() condition to the trigger clearing call, which the original GPIO_EN clearing code was missing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 23:19:57 +0100