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* pinctrl: fix allmodconfig noiseLinus Walleij2015-04-153-2/+8
| | | | | | | | There was some mess in the dependencies in the pinctrl Kconfig for compile tests under allmodconfig. Mea Culpa. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.1-1' of ↵Linus Torvalds2015-04-1582-932/+14568
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pincontrol updates from Linus Walleij: "This is the bulk of pin control changes for the v4.1 development cycle. Nothing really exciting this time: we basically added a few new drivers and subdrivers and stabilized them in linux-next. Some cleanups too. With sunrisepoint Intel has a real fine fully featured pin control driver for contemporary hardware, and the AMD driver is also for large deployments. Most of the others are ARM devices. New drivers: - Intel Sunrisepoint - AMD KERNCZ GPIO - Broadcom Cygnus IOMUX New subdrivers: - Marvell MVEBU Armada 39x SoCs - Samsung Exynos 5433 - nVidia Tegra 210 - Mediatek MT8135 - Mediatek MT8173 - AMLogic Meson8b - Qualcomm PM8916 On top of this cleanups and development history for the above drivers as issues were fixed after merging" * tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: sirf: move sgpio lock into state container pinctrl: Add support for PM8916 GPIO's and MPP's pinctrl: bcm2835: Fix support for threaded level triggered IRQs sh-pfc: r8a7790: add EtherAVB pin groups pinctrl: Document "function" + "pins" pinmux binding pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support pinctrl: fsl: imx: Check for 0 config register pinctrl: Add support for Meson8b documentation: Extend pinctrl docs for Meson8b pinctrl: Cleanup Meson8 driver Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion. pinctrl: at91: convert __raw to endian agnostic IO pinctrl: constify of_device_id array pinctrl: pinconf-generic: add dt node names to error messages pinctrl: pinconf-generic: scan also referenced phandle node pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver pinctrl: st: Display pin's function when printing pinctrl debug information pinctrl: st: Show correct pin direction also in GPIO mode pinctrl: st: Supply a GPIO get_direction() call-back pinctrl: st: Move st_get_pio_control() further up the source file ...
| * pinctrl: sirf: move sgpio lock into state containerLinus Walleij2015-04-091-12/+12
| | | | | | | | | | | | | | Instead of referring to a global static variable for the sgpio locking, use the state container to contain the lock. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Add support for PM8916 GPIO's and MPP'sIvan T. Ivanov2015-04-082-0/+2
| | | | | | | | | | | | | | | | Add compatible string definitions and supported pin functions. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm2835: Fix support for threaded level triggered IRQsCharles Keepax2015-04-081-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | Currently, the driver uses handle_simple_irq for all IRQ types and hard codes the acknowledge for different IRQ types into the handler. It is better to use the IRQ core as intended and let it handle the differences between the various types of IRQ. For example the current system does not work for threaded level triggered IRQs as these need to be masked until the threaded handler has run. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * sh-pfc: r8a7790: add EtherAVB pin groupsSergei Shtylyov2015-04-071-0/+91
| | | | | | | | | | | | | | | | | | | | Add EtherAVB pin groups to R8A7790 PFC driver. Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO supportMika Westerberg2015-04-075-0/+1632
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO interrupts). The driver is split into core and platform parts so that the same core driver can be reused in other drivers for other Intel GPIO hardware that is based on the same host controller design. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: fsl: imx: Check for 0 config registerMarkus Pargmann2015-04-071-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 is used in all pinfunction definitions when a config register is not available, for example imx25-pinfunc.h. If a configuration value is used for such a pinfunction the driver will always write it to the configuration register if it is not -1. For a 0 configuration register the configuration value is written to offset 0x0. This can lead to a crashing/hanging system without any warning message. This patch checks for 0 config register and sets the internal value to -1. If the configuration value is not NO_PADCTL this leads to an error message that applying the configuration failed. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Add support for Meson8bCarlo Caione2015-04-074-1/+905
| | | | | | | | | | | | | | | | This patch adds support for the AmLogic Meson8b SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * documentation: Extend pinctrl docs for Meson8bCarlo Caione2015-04-071-2/+3
| | | | | | | | | | | | | | | | | | Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Cleanup Meson8 driverCarlo Caione2015-04-072-597/+461
| | | | | | | | | | | | | | | | | | | | This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Fix inconsistent spinlock of AMD GPIO driver which can beKen Xue2015-04-072-16/+15
| | | | | | | | | | | | | | | | recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion. Signed-off-by: Ken Xue <Ken.Xue@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: convert __raw to endian agnostic IOBen Dooks2015-04-071-25/+25
| | | | | | | | | | | | | | | | | | | | Use endian agnostic _relaxed IO accessors instead of the __raw ones. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Cc: Andrew Victor <linux@maxim.org.za> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: constify of_device_id arrayFabian Frederick2015-03-2732-34/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | of_device_id is always used as const. (See driver.of_match_table and open firmware functions) Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinconf-generic: add dt node names to error messagesBaruch Siach2015-03-271-2/+4
| | | | | | | | | | | | | | This makes the error message much more useful. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinconf-generic: scan also referenced phandle nodeBaruch Siach2015-03-271-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node directly referenced by phandle, not only its child nodes. The "parent scan" feature needs a few other changes: * Move the pinconf_generic_dt_node_to_map() error handling code to a common place, under the 'exit' label. * Move the pins/groups strings count earlier in pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when these properties are missing or wrong Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driverThomas Petazzoni2015-03-271-0/+40
| | | | | | | | | | | | | | | | This commit adds suspend/resume support to the Armada XP pinctrl driver, by simply saving and restoring the MPP registers. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Display pin's function when printing pinctrl debug informationLee Jones2015-03-251-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Great for easily determining which mode a pin is operating in. This patch was particularly helpful when debugging a recent GPIO/ Pinctrl disparity issue. Before: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] After [GPIO]: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] After [Alt]: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2 [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Show correct pin direction also in GPIO modeLee Jones2015-03-251-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now ST's pinconf_dbg_show() call-back has displayed the PIO alternate function direction, which is only relevant if a pin is operating in an alternate function mode i.e not GPIO mode. If a pin is in GPIO mode its direction is both set and status is obtained by a completely different/unrelated bunch of registers. This change ensures that the correct pin direction is shown, even if a pin is operating in GPIO mode. Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Supply a GPIO get_direction() call-backLee Jones2015-03-251-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ST's hardware differentiates between GPIO mode and Pinctrl alternate functions. When a pin is in GPIO mode, there are dedicated registers to set and obtain direction status. However, If a pin's alternate function is in use then the direction is set and status is derived from a bunch of syscon registers. The issue is; until now there was a lack of parity between the two. For example: Catting the two following information sources could result in conflicting information (output has been snipped for simplicity): $ cat /sys/kernel/debug/gpio GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4: gpio-33 (? ) out hi $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] In this example GPIO-33 is a GPIO controlled LED, which is set for output, as you'd expect. However, when the same information is drafted from Pinctrl, it clearly states that OE (Output Enable) is not set i.e. the pin is set for input. This is because OE normally only represents alternate functions and has no bearing on how the pin operates when in Alt-0 (GPIO mode). This patch changes the current semantics and provides a parity link between the two subsystems. The get_direction() call-back firstly determines which function a pin is operating in, then uses the appropriate helpers for that mode. Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Move st_get_pio_control() further up the source fileLee Jones2015-03-251-10/+10
| | | | | | | | | | | | | | | | | | | | st_get_pio_control() will be used by subsequent calls which are to be located above its original position. This is required to prevent the need for an unnecessary forward-declaration/prototype. Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: st: Introduce a 'get pin function' callLee Jones2015-03-251-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | This call fetches the numerical function value a specified pin is currently operating in. Function zero is more often than not the GPIO function. Greater than zero values represent an alternative function. You'd need to either look those up in the Device Tree sources or the Programmer's Manual. Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: use signed bitfields for optional fieldsStefan Agner2015-03-191-20/+20
| | | | | | | | | | | | | | | | | | | | Optional fields are set to -1 by various preprocessor macros. Make sure the fields can actually store them. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mt8135/mt8173: Constify of_device_id tableAxel Lin2015-03-182-10/+6
| | | | | | | | | | | | | | | | Also make the table a bit compact. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mtk-common: Use devm_kcalloc at appropriate placesAxel Lin2015-03-181-10/+7
| | | | | | | | | | | | | | | | Prefer devm_kcalloc over devm_kzalloc with multiply. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mt8135/mt8173: Fix build error due to missing include fileAxel Lin2015-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below build error: CC drivers/pinctrl/mediatek/pinctrl-mt8135.o In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory compilation terminated. make[3]: *** [drivers/pinctrl/mediatek/pinctrl-mt8135.o] Error 1 make[2]: *** [drivers/pinctrl/mediatek] Error 2 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: Adjust mt8173 pinctrl kconfigYingjoe Chen2015-03-181-3/+8
| | | | | | | | | | | | | | | | | | | | ARM64 maintainer doesn't want to add MACH_* for each SoC. Adjust mt8173 pinctrl kconfig entry so user can manually select it. Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mtk-common: Remove kfreeAxel Lin2015-03-181-4/+2
| | | | | | | | | | | | | | | | Remove erroneous kfree for memory allocated by devm_kzalloc Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: Fix include directiveGuenter Roeck2015-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build failure: In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory seen when building arm:multi_v7_defconfig. Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Remove r8a7790 platform_device_id entryGeert Uytterhoeven2015-03-181-3/+0
| | | | | | | | | | | | | | | | | | | | The r8a7790 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Remove emev2 platform_device_id entryGeert Uytterhoeven2015-03-181-3/+0
| | | | | | | | | | | | | | | | | | | | The emev2 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Use u32 to store register addressesGeert Uytterhoeven2015-03-183-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all PFC registers lie in low 32-bit address space. Hence use u32 instead of unsigned long to store PFC register addresses in pinctrl tables. All calculations of virtual addresses use a phys_addr_t intermediate, so we know where to add an offset if the 32-bit assumption ever becomes false. While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a 64-bit shmobile_defconfig kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Use reg_width instead of reg as sentinelGeert Uytterhoeven2015-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | All other loops over sh_pfc_soc_info.data_regs[] use pinmux_data_reg.regwidth as the sentinel, which is safer as zero is never a valid regwidth value (reg could be zero if we start using it to store an offset). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Use unsigned int for register/field widths and offsetsGeert Uytterhoeven2015-03-183-34/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As register and field widths and offsets are in the range 1..32, use unsigned int (mostly replacing unsigned long) to store them in local variables and for passing them around. Move to one variable per line, move variables to the beginning of the block where they are used, and drop superfluous initializations while we are at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned longGeert Uytterhoeven2015-03-182-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | Register and field widths are in the range 1..32. Storing them in the pinctrl data in (arrays of) unsigned long wastes space. This decreases the size of a (32-bit) shmobile_defconfig kernel supporting 7 SoCs by 26460 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add AMD GPIO driver support.Ken Xue2015-03-184-0/+1147
| | | | | | | | | | | | | | | | | | KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl blockAbhilash Kesavan2015-03-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: "samsung-pinctrl 10580000.pinctrl: irq number not available" Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: cygnus: add gpio/pinconf driverRay Jui2015-03-183-0/+930
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO controller, the chipCommonG GPIO controller, and the always-on GPIO controller. Basic PINCONF configurations such as bias pull up/down, and drive strength are also supported in this driver. Pins from the ASIU GPIO controller can be individually muxed to GPIO function, through interaction with the Cygnus IOMUX controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Tested-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: fix build errorHongzhou Yang2015-03-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to pinconf_generic_parse_dt_config() API changes in pinctrl devel branch, add one parameter to fix build error. Also fix warning: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning: too many arguments for format [-Wformat-extra-args] dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret); ^ by removing extra parameter when calling dev_err in mtk_pctrl_init. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: emulate GPIO interrupt on both-edgesYingjoe Chen2015-03-184-3/+83
| | | | | | | | | | | | | | | | | | | | | | | | MTK EINT does not support generating interrupt on both edges. Emulate this by changing edge polarity while enable irq, set types and interrupt handling. This follows an example of drivers/gpio/gpio-mxc.c. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * arm64: mediatek: Add Pinctrl/GPIO/EINT driver for mt8173.Hongzhou Yang2015-03-186-0/+1704
| | | | | | | | | | | | | | | | | | Add mt8173 support using mediatek common pinctrl driver. MT8173 have a different ies_smt setting register than mt8135, so adding this support to common code. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: Add EINT support to MTK pinctrl driver.Maoguang Meng2015-03-183-2/+435
| | | | | | | | | | | | | | | | | | MTK SoC support external interrupt(EINT) from most SoC pins. Add EINT support to pinctrl driver. Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.Hongzhou Yang2015-03-188-0/+3470
| | | | | | | | | | | | | | | | | | | | | | | | | | The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sh-pfc: Use u32 to store register dataGeert Uytterhoeven2015-03-183-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly replacing unsigned long) to store (parts of) register values and masks. Switch the shadow register operations from {set,clear}_bit() to plain C bit operations, as the former can operate on long data only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: cygnus: add initial IOMUX driver supportRay Jui2015-03-183-2/+1038
| | | | | | | | | | | | | | | | | | | | | | This adds the initial driver support for the Broadcom Cygnus IOMUX controller. The Cygnus IOMUX controller supports group based mux configuration but allows certain pins to be muxed to GPIO individually Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Tested-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm: consolidate Broadcom pinctrl driversRay Jui2015-03-186-22/+29
| | | | | | | | | | | | | | Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: do not implicitly set pin regs to -1Stefan Agner2015-03-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Commit 3dac1918a491 ("pinctrl: imx: detect uninitialized pins") needs the values in struct imx_pin_reg to be -1. This has been done in a rather unorthodox way by setting the memory to 0xff using memset... Use a proper for loop to initialize the whole array with -1. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: handle input-enable pinconf propertyStanimir Varbanov2015-03-091-0/+11
| | | | | | | | | | | | | | | | | | | | This enables support of 'input-enable' pinconf generic property in the pinctrl driver. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: enable generic pinconfStanimir Varbanov2015-03-091-4/+2
| | | | | | | | | | | | | | | | | | | | | | This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91: simplify probe error handlingBaruch Siach2015-03-091-5/+1
| | | | | | | | | | | | | | | | | | There is no code ender the 'err' label. Just return the error code directly. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 07:10:48 +0100