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* pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handlerAlexander Stein2017-01-301-0/+2
| | | | | | | | | | | | According to VLI64 Intel Atom E3800 Specification Update (#329901) concurrent read accesses may result in returning 0xffffffff and write accesses may be dropped silently. To workaround all accesses must be protected by locks. Cc: stable@vger.kernel.org Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: Debounce register is one per communityAndy Shevchenko2017-01-301-3/+10
| | | | | | | | | | | | | | | | | | | | | | | Debounce value is set globally per community. Otherwise user will easily get a kernel crash when they start using the feature: BUG: unable to handle kernel paging request at ffffc900003be000 IP: byt_gpio_dbg_show+0xa9/0x430 Make it clear in byt_gpio_reg(). Note that this fix just prevents kernel to crash, but doesn't make any difference to the existing logic. It means the last caller will win the trade and debounce value will be configured accordingly. The actual logic fix needs to be thought about and it's not as important as crash fix. That's why the latter goes separately and right now. Fixes: 658b476c742f ("pinctrl: baytrail: Add debounce configuration") Cc: Cristina Ciocan <cristina.ciocan@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: Rectify debounce support (part 2)Andy Shevchenko2017-01-301-4/+8
| | | | | | | | | | | | | | | The commit 04ff5a095d66 ("pinctrl: baytrail: Rectify debounce support") almost fixes the logic of debuonce but missed couple of things, i.e. typo in mask when disabling debounce and lack of enabling it back. This patch addresses above issues. Reported-by: Jean Delvare <jdelvare@suse.de> Fixes: 04ff5a095d66 ("pinctrl: baytrail: Rectify debounce support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: merrifield: Add missed check in mrfld_config_set()Andy Shevchenko2017-01-301-0/+3
| | | | | | | | | | Not every pin can be configured. Add missed check to prevent access violation. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Don't enforce bias disable (for now)Maxime Ripard2017-01-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 07fe64ba213f ("pinctrl: sunxi: Handle bias disable") actually enforced enforced the disabling of the pull up/down resistors instead of ignoring it like it was done before. This was part of a wider rework to switch to the generic pinconf bindings, and was meant to be merged together with DT patches that were switching to it, and removing what was considered default values by both the binding and the boards. This included no bias on a pin. However, those DT patches were delayed to 4.11, which would be fine only for a significant number boards having the bias setup wrong, which in turns break the MMC on those boards (and possibly other devices too). In order to avoid conflicts as much as possible, bring back the old behaviour for 4.10, and we'll revert that commit once all the DT bits will have landed. Tested-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: berlin-bg4ct: fix the value for "sd1a" of pin SCRD0_CRD_PRESJisheng Zhang2017-01-301-1/+1
| | | | | | | This should be a typo. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20Masahiro Yamada2017-01-191-1/+1
| | | | | | | | Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins. Fixes: 1e359ab1285e ("pinctrl: uniphier: add Ethernet pin-mux settings") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXMMartin Blumenstingl2017-01-192-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The GXBB and GXL/GXM pinctrl drivers had a configuration which conflicts with uart_ao_a. According to the GXBB ("S905") datasheet the AO UART functions are: - GPIOAO_0: Func1 = UART_TX_AO_A (bit 12), Func2 = UART_TX_AO_B (bit 26) - GPIOAO_1: Func1 = UART_RX_AO_A (bit 11), Func2 = UART_RX_AO_B (bit 25) - GPIOAO_4: Func2 = UART_TX_AO_B (bit 24) - GPIOAO_5: Func2 = UART_RX_AO_B (bit 25) The existing definition for uart_AO_A already uses GPIOAO_0 and GPIOAO_1. The old definition of uart_AO_B however was broken, as it used GPIOAO_0 for TX (which would be fine) and two pins (GPIOAO_1 and GPIOAO_5) for RX (which does not make any sense). This fixes the uart_AO_B configuration by moving it to GPIOAO_4 and GPIOAO_5 (it would be possible to use GPIOAO_0 and GPIOAO_1 in theory, but all existing hardware uses uart_AO_A there). The fix for GXBB and GXL/GXM is identical since it seems that these specific pins are identical on both SoC variants. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amd: avoid maybe-uninitalized warningArnd Bergmann2017-01-121-0/+2
| | | | | | | | | | | | | | | | | Since gpio_dev->hwbank_num is now a variable, the compiler cannot figure out if pin_num is initialized at all: drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_dbg_show': drivers/pinctrl/pinctrl-amd.c:210:3: warning: 'pin_num' may be used uninitialized in this function [-Wmaybe-uninitialized] for (; i < pin_num; i++) { ^~~ drivers/pinctrl/pinctrl-amd.c:172:21: warning: 'i' may be used uninitialized in this function [-Wmaybe-uninitialized] This adds a 'default' statement to make that case well-defined. Fixes: 3bfd44306c65 ("pinctrl: amd: Add support for additional GPIO") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: Do not add all GPIOs to IRQ domainAndy Shevchenko2017-01-121-3/+8
| | | | | | | | | | | | | | | | | | | | When DIRECT_IRQ_EN is set, the pin is routed directly to the IO-APIC bypassing the GPIO driver completely. However, the mask register is still used to determine if the pin is supposed to generate IRQ or not. So with commit 3ae02c14d964 the IRQ core masks all IRQs (because of handle_bad_irq()) the pin connected to the touchscreen gets masked as well and hence no interrupts. To make this all work as expected we do not add those GPIOs to the IRQ domain that can actually propagate interrupts. Fixes: 3ae02c14d964 ("pinctrl: intel: set default handler to be handle_bad_irq()") Reported-by: Robert R. Howell <rhowell@uwyo.edu> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: Rectify debounce supportAndy Shevchenko2017-01-111-11/+17
| | | | | | | | | | | | | | | | | | | | The commit 658b476c742f ("pinctrl: baytrail: Add debounce configuration") implements debounce for Baytrail pin control, but seems wasn't tested properly. The register which keeps debounce value is separated from the configuration one. Writing wrong values to the latter will guarantee wrong behaviour of the driver and even might break something physically. Besides above there is missed case how to disable it, which is actually done through the bit in configuration register. Rectify implementation here by using proper register for debounce value. Fixes: 658b476c742f ("pinctrl: baytrail: Add debounce configuration") Cc: Cristina Ciocan <cristina.ciocan@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Set pin direction properlyAndy Shevchenko2017-01-111-11/+19
| | | | | | | | | | | | | | | There are two bits in the PADCFG0 register to configure direction, one per TX/RX buffers. For now we wrongly assume that the GPIO is always requested before it is being used, which is not true when the GPIO is used through irqchip. In this case the GPIO is never requested and we never enable RX buffer for it. Fix this by setting both bits accordingly. Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: broxton: Use correct PADCFGLOCK offsetMika Westerberg2017-01-111-1/+1
| | | | | | | | | PADCFGLOCK (and PADCFGLOCK_TX) offset in Broxton actually starts at 0x060 and not 0x090 as used in the driver. Fix it to use the correct offset. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433Chanwoo Choi2016-12-302-40/+82
| | | | | | | | | | | | | | | | | This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433 because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV. Fixes: 3c5ecc9ed353 ("pinctrl: exynos: Add support for Exynos5433") Cc: stable@vger.kernel.org Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene@kernel.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson: fix gpio request disabling other modesNeil Armstrong2016-12-291-1/+1
| | | | | | | | | | | | | | The pinctrl_gpio_request is called with the "full" gpio number, already containing the base, then meson_pmx_request_gpio is then called with the final pin number. Remove the base addition when calling meson_pmx_disable_other_groups. Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs") CC: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/amd: Set the level based on ACPI tablesShyam Sundar S K2016-12-291-12/+7
| | | | | | | | | | | | | In the function amd_gpio_irq_set_type, read the values from the ACPI table to set the level and drop the settings passed by the client. Cc: <stable@vger.kernel.org> # 4.8.x+ Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Reviewed-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2016-12-161-6/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together. We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board: - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors These are commercially available consumer platforms we now support: - Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385 And a couple of new boards targeted at developers, makers or industrial integration: - Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module Other changes: - added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq - Continued fixes for W=1 dtc warnings - The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST - The exynos4415 dtsi file is removed as nothing uses it. - Intel PXA25x can now be booted using devicetree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...
| * Merge tag 'arm-soc/for-4.10/devicetree' of ↵Arnd Bergmann2016-11-301-6/+0
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://github.com/Broadcom/stblinux into next/dt Pull "Broadcom devicetree changes for 4.10" from Florian Fainelli: This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10, please pull the following: - Rafal adds support for the Netgear R8500 routers, adds basic support for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex A7). He also enables the UART on the Netgear R8000 and restructures the include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes which enables USB 3.0 on BCM5301X devices that support it. Finally he adds support for the TP-LINK Archer C9 V1 router. - Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates the bcm958625k reference board to have it enabled - Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using a BCM47094) - Scott fixes the pinctrl names in the Cygnus DTS files - Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds the node for the OTP controller found on Cygnus SoCs - Dhananjay enables the GPIO B controller on Norstarh Plus SoCs - Eric defines standard pinctrl groups in the BCM2835 GPIO node - Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes to use their appropriate pinctrl functions - Linus adds names for the Raspberry Pi GPIO lines based on the datasheet - Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block - Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally adds names for the Raspberry Zero GPIO lines * tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux: (29 commits) ARM: bcm2835: Add names for the RPi Zero GPIO lines ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ARM: dts: enable GPIO-b for Broadcom NSP ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1 ARM: dts: Add node for Broadcom OTP controller driver ARM: dts: Enable interrupt support for cygnus crmu gpio driver ARM: dts: Enable Broadcom iProc mailbox controller ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ARM: bcm2835: dts: add thermal node to device-tree of bcm283x dt: bindings: add thermal device driver for bcm2835 ARM: dts: bcm283x: fix typo in mailbox address DT: binding: bcm2835-mbox: fix address typo in example ARM: dts: cygnus: fix naming of pinctrl node ARM: BCM53573: Specify PMU and its ILP clock in the DT ARM: BCM5301X: Add DT for Luxul XWR-3100 ARM: BCM5301X: Add DT for Luxul XAP-1510 ARM: BCM5301X: Specify USB 3.0 PHY in DT ARM: BCM5301X: Enable UART on Netgear R8000 ARM: BCM5301X: Add separated DTS include file for BCM47094 ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes ...
| | * pinctrl: bcm2835: add pull defines to dt bindingsGerd Hoffmann2016-10-171-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also delete (unused) private enum from driver. The pull defines can be used instead if needed. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
* | | Merge tag 'pinctrl-v4.10-1' of ↵Linus Torvalds2016-12-1366-1345/+5688
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pinctrl updates from Linus Walleij: "Bulk pin control changes for the v4.10 kernel cycle: No core changes this time. Mainly gradual improvement and feature growth in the drivers. New drivers: - New driver for TI DA850/OMAP-L138/AM18XX pinconf - The SX150x was moved over from the GPIO subsystem and reimagined as a pin control driver with GPIO support in a joint effort by three independent users of this hardware. The result was amazingly good! - New subdriver for the Oxnas OX820 Improvements: - The sunxi driver now supports the generic pin control bindings rather than the sunxi-specific. Add debouncing support to the driver. - Simplifications in pinctrl-single adding a generic parser. - Two downstream fixes and move the Raspberry Pi BCM2835 over to use the generic GPIOLIB_IRQCHIP" * tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (92 commits) pinctrl: sx150x: use new nested IRQ infrastructure pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505 pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced' pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147] pinctrl: mt8173: set GPIO16 to usb iddig mode pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf devicetree: bindings: pinctrl: Add binding for ti,da850-pupd Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition pinctrl: intel: set default handler to be handle_bad_irq() pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507 pinctrl: sx150x: sort chips by part number pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508) pinctrl: imx: fix imx_pinctrl_desc initialization pinctrl: sx150x: support setting multiple pins at once pinctrl: sx150x: various spelling fixes and some white-space cleanup pinctrl: mediatek: use builtin_platform_driver pinctrl: stm32: use builtin_platform_driver pinctrl: sunxi: Testing the wrong variable pinctrl: nomadik: split up and comments MC0 pins ...
| * | | pinctrl: sx150x: use new nested IRQ infrastructureLinus Walleij2016-12-071-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip() calls to properly created a nested irqchip and mark all child irqs properly with their parent IRQ. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505Peter Rosin2016-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem where sx150x_regmap_reg_width() returns 8 for the data register (reg 0) for sx1504 where it should return 4, and return a correct 8 for sx1505 but for the wrong reason (both chips lack the 'advanced' register). This is not a real problem, since nothing depends on the function returning 4 or 8, and certainly not if it is returning 8 for the wrong reason. But fix this to avoid nasty surprises down the line. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'Peter Rosin2016-12-071-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the datasheets and is less confusing since the register has nothing to with advancing anything. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]Peter Rosin2016-12-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code assumes 8-bit or 16-bit width registers, but three of the chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as well, they leave the high part of each register unused. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mt8173: set GPIO16 to usb iddig modeChunfeng Yun2016-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the default mode of GPIO16 pin is gpio, when set EINT16 to IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be fixed when set its default mode as usb iddig. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: bcm2835: switch to GPIOLIB_IRQCHIPLinus Walleij2016-12-072-76/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It should be possible to use the GPIOLIB_IRQCHIP helper library with the BCM2835 driver since it is a pretty straight forward cascaded irqchip. The only difference from other drivers is that the BCM2835 has several banks for a single gpiochip, and each bank has a separate IRQ line. Instead of creating one gpiochip per bank, a single gpiochip covers all banks GPIO lines. This makes it necessary to resolve the bank ID in the IRQ handler. The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off the same gpiochip by calling gpiochip_set_chained_irqchip() repeatedly, but we have been a bit short on examples for how this should be handled in practice, so this is intended as an example of how this can be achieved. The old code did not model the chip as a chained interrupt handler, but this patch also rectifies that situation. Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Eric Anholt <eric@anholt.net> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconfDavid Lechner2016-12-073-0/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: intel: set default handler to be handle_bad_irq()Andy Shevchenko2016-12-072-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507Peter Rosin2016-11-251-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Untested, register offsets carefully copied from datasheets. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: sort chips by part numberPeter Rosin2016-11-251-71/+71
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)Peter Rosin2016-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All other registers on these chips are 8-bit, but reg_sense is 16-bits and therefore needs to be moved down one notch. This was apparently overlooked in the conversion to regmap, which only updated the register locations for the 16-bit chips. Fixes: 6489677f86c3 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API") Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: imx: fix imx_pinctrl_desc initializationGary Bisson2016-11-251-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: 6e408ed8be0e ("pinctrl: imx: fix initialization of imx_pinctrl_desc") Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: support setting multiple pins at oncePeter Rosin2016-11-241-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the chip does not have an oscio pin, all pins are configured in the same regmap register making it trivial to update all pins at once, so do that. If an oscio pin is present, there needs to be more locking in place to handle all cases correctly, so this is skipped. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: various spelling fixes and some white-space cleanupPeter Rosin2016-11-231-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: use builtin_platform_driverGeliang Tang2016-11-221-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: stm32: use builtin_platform_driverGeliang Tang2016-11-221-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sunxi: Testing the wrong variableDan Carpenter2016-11-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smatch complains that we dereference "map" before testing it for NULL which is true. We should be testing "*map" instead. Also on the error path, we should free *map and set it to NULL. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: nomadik: split up and comments MC0 pinsLinus Walleij2016-11-181-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When debugging it helps to see exactly which pin goes where, so make it very detailed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: single: Fix a couple error codesDan Carpenter2016-11-161-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should return -ENOMEM instead of success if pcs_add_function() fails. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sunxi: fix theoretical uninitialized variable accessArnd Bergmann2016-11-161-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc warns about a way that it could use an uninitialized variable: drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init': drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized] This cannot really happen except if 'freq' is UINT_MAX and 'clock' is zero, and both of these are forbidden. To shut up the warning anyway, this changes the logic to initialize the return code to the first divider value before looking at the others. Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'sh-pfc-for-v4.10-tag2' of ↵Linus Walleij2016-11-167-366/+816
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 (take two) - DU and EtherAVB pin groups for R-Car M3-W, - Bias handling cleanups and bug fixes, - Drive-strength for non-GPIO pins for R-Car H3, - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
| | * | | pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pinsNiklas Söderlund2016-11-161-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other than QSPI, but their drive strength can be controlled. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pinsNiklas Söderlund2016-11-161-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable ↵Niklas Söderlund2016-11-161-15/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drive-strength There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT by function names and their drive-strength modified. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: Support named pins with custom configurationNiklas Söderlund2016-11-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pins not associated with a GPIO port can still have other configuration parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named pins to be declared with a set of configurations. The new macro is an modification of SH_PFC_PIN_NAMED to allow for optional configuration to be assigned. The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be used to define pins not associated with a GPIO port. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: r8a7778: Use lookup function for bias dataNiklas Söderlund2016-11-161-170/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: r8a7795: Use lookup function for bias dataNiklas Söderlund2016-11-161-171/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: r8a7795: Simplify get bias logicNiklas Söderlund2016-11-161-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last else statement is missing braces, and the indentation level can be reduced. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: Add helper to handle bias lookup tableNiklas Söderlund2016-11-153-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some SoC there are no simple mapping of pins to bias register bits and a lookup table is needed. This logic is already implemented in some SoC specific drivers that could benefit from a generic implementation. Add helpers to deal with the lookup which later can be used by the SoC specific drivers. The logic used to lookup are different from the one it aims to replace, this is intentional. This new method reduces the memory consumption at the cost of increased CPU usage and fix a bug where a WARN() would incorrectly be triggered if the register offset is 0. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLENiklas Söderlund2016-11-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if the operation get_bias() is implemented but the pin is not handled by the get_bias() implementation. In that case the output will state that "input bias disabled" indicating that this pin has bias control support. Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also solves the issue where SoC specific implementations print error messages if their particular implementation of {set,get}_bias() is called with a pin it does not know about. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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