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* Merge tag 'sh-pfc-for-v5.1-tag2' of ↵Linus Walleij2019-02-137-5/+677
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.1 (take two) - Add DRIF (digital radio) pin groups on R-Car E3 and M3-N, - Add TMU (timer) pin groups on R-Car M3-N, - Miscellaneous fixes, - Build-time validation for fixed-size field width mismatches.
| * pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functionsTakeshi Kihara2019-02-111-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Based on a similar patch of the R8A7796 PFC driver by Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functionsTakeshi Kihara2019-02-111-0/+48
| | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Validate fixed-size field widths at build timeGeert Uytterhoeven2019-02-111-1/+2
| | | | | | | | | | | | | | | | | | Add a build-time check, to ensure the register and field widths in descriptors for config registers with fixed-width fields are sane. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groupsGeert Uytterhoeven2019-02-111-1/+2
| | | | | | | | | | | | | | | | | | There are two pin groups for the FSIC SPDIF signal, but the FSIC pin group array lists only one, and it refers to a nonexistent group. Fixes: 2ecd4154c906b7d6 ("sh-pfc: sh73a0: Add FSI pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin groupGeert Uytterhoeven2019-02-111-0/+1
| | | | | | | | | | | | | | | | | | The vin1_data18_b pin group itself is present, but it is not listed in the VIN1 pin group array, and thus cannot be selected. Fixes: 7dd74bb1f058786e ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin groupGeert Uytterhoeven2019-02-111-1/+1
| | | | | | | | | | | | | | | | | | The entry for "scifb2_data_c" in the SCIFB2 pin group array contains a typo, thus the group cannot be selected. Fixes: 5088451962389924 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: emev2: Add missing pinmux functionsGeert Uytterhoeven2019-02-111-0/+20
| | | | | | | | | | | | | | | | | | The err_rst_reqb, ext_clki, lowpwr, and ref_clko pin groups are present, but no pinmux functions refer to them, hence they can not be selected. Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functionsTakeshi Kihara2019-02-051-2/+253
| | | | | | | | | | | | | | | | | | This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | pinctrl: sunxi: Support I/O bias voltage setting on A80Chen-Yu Tsai2019-02-114-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A80 SoC has configuration registers for I/O bias voltage. Incorrect settings would make the affected peripherals inoperable in some cases, such as Ethernet RGMII signals biased at 2.5V with the settings still at 3.3V. However low speed signals such as MDIO on the same group of pins seem to be unaffected. Previously there was no way to know what the actual voltage used was, short of hard-coding a value in the device tree. With the new pin bank regulator supply support in place, the driver can now query the regulator for its voltage, and if it's valid (as opposed to being the dummy regulator), set the bias voltage setting accordingly. Add a quirk to denote the presence of the configuration registers, and a function to set the correct setting based on the voltage read back from the regulator. This is only done when the regulator is first acquired and enabled. While it would be nice to have a notifier on the regulator so that when the voltage changes, the driver can update the setting, in practice no board currently supports dynamic changing of the I/O voltages. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'v5.0-rc6' into develLinus Walleij2019-02-116-29/+37
|\ \ | | | | | | | | | Linux 5.0-rc6
| * | pinctrl: sunxi: Correct number of IRQ banks on H6 main pin controllerChen-Yu Tsai2019-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H6 main pin controller has four banks of interrupt-triggering pins. The driver as originally submitted only specified three, but had pin descriptions referencing a fourth bank. This results in a out-of-bounds access into .irq_array of struct sunxi_pinctrl. This however did not result in a crash until v4.20, with commit a66d972465d1 ("devres: Align data[] to ARCH_KMALLOC_MINALIGN"), which changed the alignment of memory region returned by devm_kcalloc(). The increase likely moved the out-of-bounds access into the next, unmapped page. With KASAN on, the bug is quite clear: BUG: KASAN: slab-out-of-bounds in sunxi_pinctrl_init_with_variant+0x49c/0x12b8 Write of size 4 at addr ffff80002c680280 by task swapper/0/1 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc1-00016-gc480a5e6a077 #3 Hardware name: OrangePi Lite2 (DT) Call trace: dump_backtrace+0x0/0x220 show_stack+0x14/0x20 dump_stack+0xac/0xd4 print_address_description+0x60/0x25c kasan_report+0x14c/0x1ac __asan_store4+0x80/0xa0 sunxi_pinctrl_init_with_variant+0x49c/0x12b8 h6_pinctrl_probe+0x18/0x20 platform_drv_probe+0x6c/0xc8 really_probe+0x244/0x4b0 driver_probe_device.part.4+0x11c/0x164 __driver_attach+0x120/0x190 bus_for_each_dev+0xe8/0x158 driver_attach+0x30/0x40 bus_add_driver+0x308/0x318 driver_register+0xbc/0x1d0 __platform_driver_register+0x7c/0x88 h6_pinctrl_driver_init+0x18/0x20 do_one_initcall+0xd4/0x208 kernel_init_freeable+0x230/0x2c8 kernel_init+0x10/0x108 ret_from_fork+0x10/0x1c Allocated by task 1: kasan_kmalloc.part.0+0x4c/0x100 kasan_kmalloc+0xc4/0xe8 kasan_slab_alloc+0x14/0x20 __kmalloc_track_caller+0x130/0x238 devm_kmalloc+0x34/0xd0 sunxi_pinctrl_init_with_variant+0x1d8/0x12b8 h6_pinctrl_probe+0x18/0x20 platform_drv_probe+0x6c/0xc8 really_probe+0x244/0x4b0 driver_probe_device.part.4+0x11c/0x164 __driver_attach+0x120/0x190 bus_for_each_dev+0xe8/0x158 driver_attach+0x30/0x40 bus_add_driver+0x308/0x318 driver_register+0xbc/0x1d0 __platform_driver_register+0x7c/0x88 h6_pinctrl_driver_init+0x18/0x20 do_one_initcall+0xd4/0x208 kernel_init_freeable+0x230/0x2c8 kernel_init+0x10/0x108 ret_from_fork+0x10/0x1c Freed by task 0: (stack is not available) The buggy address belongs to the object at ffff80002c680080 which belongs to the cache kmalloc-512 of size 512 The buggy address is located 0 bytes to the right of 512-byte region [ffff80002c680080, ffff80002c680280) The buggy address belongs to the page: page:ffff7e0000b1a000 count:1 mapcount:0 mapping:ffff80002e00c780 index:0xffff80002c683c80 compound_mapcount: 0 flags: 0x10200(slab|head) raw: 0000000000010200 ffff80002e003a10 ffff80002e003a10 ffff80002e00c780 raw: ffff80002c683c80 0000000000100001 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff80002c680180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffff80002c680200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffff80002c680280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ^ ffff80002c680300: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffff80002c680380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc Correct the number of IRQ banks so there are no more mismatches. Fixes: c8a830904991 ("pinctrl: sunxi: add support for the Allwinner H6 main pin controller") Cc: <stable@vger.kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mcp23s08: spi: Fix regmap allocation for mcp23s18Jason Kridner2019-01-211-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes issue created by 9b3e4207661e67f04c72af15e29f74cd944f5964. It wasn't possible for one_regmap_config to be non-NULL at the point it was tested for mcp23s18 devices. Applied the same pattern of allocating one_regmap_config using devm_kmemdump() and then initializing the local regmap structure from that. Signed-off-by: Jason Kridner <jdk@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cherryview: fix Strago DMI workaroundDmitry Torokhov2019-01-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Well, hopefully 3rd time is a charm. We tried making that check DMI_BIOS_VERSION and DMI_BOARD_VERSION, but the real one is DMI_PRODUCT_VERSION. Fixes: 86c5dd6860a6 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197953 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1631930 Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Consider pin_base when calculating regulator array indexChen-Yu Tsai2019-01-142-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen), while R_PIO covers PL to PN. The regulator array only has space for 12 entries, which was designed to cover PA to PL. On the A80, the pin banks go up to PN, which would be the 14th entry in the regulator array. However since the driver only needs to track regulators for its own pin banks, the array only needs to have 9 entries, and also take in to account the value of pin_base, such that the regulator for the first pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry of the array. Base the regulator array index on pin_base, such that "PA" for PIO and "PL" for R_PIO both take the first element within their respective device's regulator array. Also decrease the size of the regulator array to 9, just enough to cover "PA" to "PI". Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Fix and simplify pin bank regulator handlingChen-Yu Tsai2019-01-141-20/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new per-pin-bank regulator handling code in the sunxi pinctrl driver has mismatched conditions for enabling and disabling the regulator: it is enabled each time a pin is requested, but only disabled when the pin-bank's reference count reaches zero. Since we are doing reference counting already, there's no need to enable the regulator each time a pin is requested. Instead we can just do it for the first requested pin of each pin-bank. Thus we can reverse the test and bail out early if it's not the first occurrence. Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators") Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: fix Kconfig build errors for moore coreRyder Lee2019-01-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on i386 or x86_64: Lots of build errors for drivers/pinctrl/mediatek/pinctrl-moore.c when CONFIG_OF is not enabled (but COMPILE_TEST is). first this: WARNING: unmet direct dependencies detected for PINCTRL_MTK_MOORE Depends on [n]: PINCTRL [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && OF [=n] Selected by [y]: - PINCTRL_MT7623 [=y] && PINCTRL [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && (MACH_MT7623 || COMPILE_TEST [=y]) and then: ../drivers/pinctrl/mediatek/pinctrl-moore.c:22:44: error: array type has incomplete element type static const struct pinconf_generic_params mtk_custom_bindings[] = { (etc) Fixes: b5af33df50e9 ("pinctrl: mediatek: improve Kconfig dependencies") Cc: stable@vger.kernel.org Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: ingenic: Add LCD pins for the JZ4725B SoCPaul Cercueil2019-02-081-0/+30
| | | | | | | | | | | | | | | | | | | | | Add the pins and groups for the "lcd" pin function in the JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: samsung: Remove legacy API for handling external wakeup interrupts maskKrzysztof Kozlowski2019-02-081-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the legacy, ugly API of exposing the static value of external wakeup interrupts mask, because all arch-machine users where converted to use generic implementation from pinctrl driver. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: bcm2835: Direct GPIO config changes to generic pinctrlStefan Wahren2019-02-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support GPIO config changes direct these to the generic pinctrl. This also requires an adjust of the return code for unsupported parameter otherwise gpiod_configure_flags wont work as expected. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: bcm2835: declare pin config as genericStefan Wahren2019-02-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0de704955ee44 ("pinctrl: bcm2835: Add support for generic pinctrl binding") this driver is capable to use the generic interface. So declare this accordingly. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: qcom: qcs404: Drop unused UFS_RESET macroBjorn Andersson2019-02-081-25/+0
| | | | | | | | | | | | | | | | | | | | | The UFS_RESET macro serves no purpose on QCS404, remove it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: at91: add slewrate support for SAM9X60Claudiu Beznea2019-02-082-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Add slew rate support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: at91: add compatibles for SAM9X60 pin controllerClaudiu Beznea2019-02-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add compatibles for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: at91: add drive strength support for SAM9X60Claudiu Beznea2019-02-082-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | Add drive strength support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: at91: add option to use drive strength bitsClaudiu Beznea2019-02-081-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAM9X60 uses high and low drive strengths. To implement this, in at91_pinctrl_mux_ops::set_drivestrength and at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of drive strengths (1 for low, 2 for high), thus change the code to allow the usage of drive strength bit numbers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: freescale: Add imx8mm pinctrl driver supportBai Ping2019-01-303-0/+356
| | | | | | | | | | | | | | | | | | | | | | | | Add the pinctrl driver support for i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".Zhou Yanjie2019-01-301-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original code, some function names begin with "ingenic_gpio_", and some with "gpio_ingenic_". For the sake of uniform style, all of them are changed to the beginning of "ingenic_gpio_". Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.Zhou Yanjie2019-01-301-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mmc2 for JZ4770 and JZ4780: According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this part of the original code is missing. It is worth noting that JZ4770's mmc2 supports 8bit mode while JZ4780's does not, so we added the corresponding code for both models. Add nemc-wait for JZ4770 and JZ4780: Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the original code is missing. Add mac for JZ4770: JZ4770 have a mac. But this part of the original code is missing. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.Zhou Yanjie2019-01-301-58/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete uart4 and i2c3/4 from JZ4770: According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we remove it from the JZ4770 code and add a section corresponding the JZ4780. Fix bugs in i2c0/1: The pin number was wrong in the original code. Fix bugs in uart2: JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc0: JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc1: JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in nemc: JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. And add missing cs2~5 groups for JZ4770 and JZ4780. Fix bugs in cim: JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in lcd: Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: berlin: as370: use generic "pwm" as pwm function nameJisheng Zhang2019-01-281-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we could use the generic "pwm" for two or more pins, e.g pwm0_pmux: pwm0-pmux { groups = "PWM0", "PWM1"; function = "pwm"; }; Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v5.1-tag1' of ↵Linus Walleij2019-01-2812-343/+288
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.1 - Add TMU pin groups on R-Car E3, - Miscellaneous fixes and cleanups.
| * | pinctrl: sh-pfc: r8a7778: Fix HSPI pin numbers and namesGeert Uytterhoeven2019-01-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When declaring the HSPI RX1_B and TX1_B pins, two mistakes were made: - the rows and columns in the BGA pin matrix, from which the pin numbers are derived, were exchanged, - it was not taken into account that pin row labelling skips characters I, O, Q, and S. Fix the order, and the corresponding pin names. Notes: - The actual values of the pin numbers don't really matter (they just have to be unique), so the wrong order didn't have any impact, - Changing the names of the pins is user-visible, but there are no users in (upstream) DTS files. Fixes: 4f82e3ee724f1712 ("sh-pfc: Support pins not associated with a GPIO port") Fixes: 09cc76a95802e87d ("sh-pfc: r8a7778: add HSPI pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functionsTakeshi Kihara2019-01-211-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3Geert Uytterhoeven2019-01-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike R-Car M3-W, R-Car M3-N does not have DU_DOTCLKIN2, but the corresponding pin carries the DU_DOTCLKIN3 signal. Correct all references to DU_DOTCLKIN2 to fix this. This change does not have any runtime effect, as it only changes an internal enum name, and a comment. Fixes: 490e687eb8b274b5 ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groupsGeert Uytterhoeven2019-01-211-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The naming of the "b" versions of the VIN1 pin groups is a bit odd, in that the "_b" appears in the middle of the names, instead of as a suffix. Increase consistency with other SoCs by making R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N, use the recently added optional "version" argument of the VIN_DATA_PIN_GROUP() macro. Note that this breaks backwards compatibility with existing DTBs, but there are no upstream users of the "vin1_b_*" names. Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77980: Deduplicate VIN1 pin definitionsGeert Uytterhoeven2019-01-211-43/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data12 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN1 channel. This reduces kernel size by 144 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitionsGeert Uytterhoeven2019-01-211-86/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data12 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN0 and VIN1 channels. This reduces kernel size by 288 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitionsGeert Uytterhoeven2019-01-211-64/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN5 channel. This reduces kernel size by 240 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitionsGeert Uytterhoeven2019-01-211-64/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN5 channel. This reduces kernel size by 240 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7794: Initialize TDSEL register for ES1.0Wolfram Sang2019-01-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation for ES1.0 says that some bits in TDSEL must be set (ch 5.3.35 in R-Car E2 v0.5). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions and use whitelisting for ES versions known to need this. This is needed for some SD cards supporting SDR104 transfer mode. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7790: Initialize TDSEL register for ES1.0Wolfram Sang2019-01-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation for ES1.0 says that some bits in TDSEL must be set (ch 5.3.39 in R-Car H2 v0.91). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions and use whitelisting for ES versions known to need this. This is needed for some SD cards supporting SDR104 transfer mode. For me, TDSEL was not initialized by the firmware and I had problems with the card when re-inserting it. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Print pin group when debuggingGeert Uytterhoeven2019-01-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Knowing which pin group is being configured is useful information when debugging pin configuration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"Geert Uytterhoeven2019-01-211-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit f4caa6ee736fa8a46c806ba4382c16f7e5a20248. The same can be expressed better by dropping the SH_PFC_PIN_CFG_PULL_DOWN flag from the GPIO description, as it includes returning an error to the caller when trying to configure the pin for pull-down, causing: sh-pfc e6060000.pin-controller: pin_config_set op failed for pin 201 sh-pfc e6060000.pin-controller: Error applying setting, reverse things back sh-pfc e6060000.pin-controller: failed to select default state Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capabilityGeert Uytterhoeven2019-01-211-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flag from the GP6_9 GPIO description. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numberingTakeshi Kihara2019-01-211-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOD_SEL register bit numbering was different from R-Car D3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") [shimoda: split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use a macro to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numberingTakeshi Kihara2019-01-211-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOD_SEL register bit numbering was different from R-Car E3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") [shimoda: Split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use macros to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2Takeshi Kihara2019-01-211-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0Takeshi Kihara2019-01-211-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* | pinctrl: sirf: drop pointless static qualifier in sirfsoc_gpio_probeYueHaibing2019-01-281-1/+1
| | | | | | | | | | | | | | | | There is no need to have the 'sgpio' variable static since new value always be assigned before use it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-18 12:06:58 +0100