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* pinctrl: pinctrl-imx.c: Cleaning up if unsigned is less than zeroRickard Strandqvist2014-07-111-1/+1
| | | | | | | | | Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-at91.c: Cleaning up if unsigned is less than zeroRickard Strandqvist2014-07-111-1/+1
| | | | | | | | | Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: st: add IRQCHIP_SKIP_SET_WAKE flagDavid PARIS2014-07-111-0/+1
| | | | | | | | | no .irq_set_wake API is available for pinctrl-st driver. Add the IRQCHIP_SKIP_SET_WAKE flag to inform irq handler not to call this API. Signed-off-by: David Paris <david.paris@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: bcm281xx: Staticize bcm281xx_pinctrl_probeSachin Kamat2014-07-111-1/+1
| | | | | | | bcm281xx_pinctrl_probe is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Add BUS_HOLD pin biasAndy Gross2014-07-111-0/+8
| | | | | | | | This patch adds the BUS_HOLD (Keeper) bias option for pins. Signed-off-by: Andy Gross <agross@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add A23 R_PIO controller supportChen-Yu Tsai2014-07-113-0/+148
| | | | | | | | | The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add A23 PIO controller supportChen-Yu Tsai2014-07-113-0/+598
| | | | | | | | | The A23 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Remove PINCTRL_SUNXIMaxime Ripard2014-07-111-9/+6
| | | | | | | | | | The PINCTRL_SUNXI configuration was kept only to deal with the introduction of per-machine symbols and the various pintrl drivers through different tree. Now that it's not useful anymore, we can just remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Remove gpio_out function from sun5i-a13 PG0/1/2 pinsChen-Yu Tsai2014-07-111-3/+0
| | | | | | | | | The A13 user manual states pins PG0/1/2 only have GPIO input and interrupt functions. Remove the gpio_out functions for these pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add support for rk3288 pin-controllerHeiko Stübner2014-07-111-0/+73
| | | | | | | | The pin-controller of the new RK3288 contains all the quirks just added in the previous patches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: support unrouted iomuxes per bankHeiko Stübner2014-07-111-0/+11
| | | | | | | | | | | On the upcoming RK3288 SoC contain some unrouted pins in their banks. So while for example pin8 of bank5 stays pin8 with all its settings (register offset etc), pins 0 to 7 are not routed outside the SoC at all. Therefore add a flag to mark these unrouted iomuxes to prevent people from using them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: enable iomuxes from pmu spaceHeiko Stübner2014-07-111-12/+30
| | | | | | | | The upcoming rk3288 moves some iomux settings to the pmu register space. Therefore add a flag for this and adapt the mux functions accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add support for 4bit wide iomux settingsHeiko Stübner2014-07-111-8/+26
| | | | | | | | | In the upcoming rk3288 SoC some iomux settings are 4bit wide instead of the regular 2bit. Therefore add a flag to mark iomuxes as such and adapt the mux-access as well as the offset calculation accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: precalculate iomux offsetsHeiko Stübner2014-07-111-11/+45
| | | | | | | | | | An upcoming SoC introduces an interesting quirk to iomux handling making the calculation of the iomux register-offset harder. To keep the complexity down when getting/setting the mux, precalculate the actual register offset at probe-time. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: generalize bank-quirksHeiko Stübner2014-07-111-19/+39
| | | | | | | | | | | | | | Upcoming Rockchip SoCs have additional quirks to handle. Currently they would be handled by giving the bank a special compatible property. But the nature of the new quirks would require a lot of them. Also as we want to move to the separate dw_gpio driver in the future, these bank-definitions should be extended at all. Describing the bank quirks this way also enables us to deprecate the special bank compatible string for bank0 on rk3188 and simplify the handling code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: avoid duplicated calling enable_pinmux_setting for a pinFan Wu2014-07-1122-418/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: i.MX27: Remove nonexistent pad definitionsAlexander Shiyan2014-07-111-46/+0
| | | | | | | | | | Pads for PB0-PB3, PC0-PC4, PE26-PE31 and PF24-PF31 does not exist on the i.MX27 SOC. There is no reason to define them, the presence of such definitions in the DTS files is a bug. This patch removes these nonexistent pad definitions. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: i.MX27: Remove unused structure definitionAlexander Shiyan2014-07-111-6/+0
| | | | | | | | struct imx27_pinctrl_private is not used in the driver. Remove this definition. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add i.MX1 pincontrol driverAlexander Shiyan2014-07-113-0/+287
| | | | | | | | This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Fix multi bank interrupt support in gpio_to_irqChen-Yu Tsai2014-07-111-2/+5
| | | | | | | | | | | | | | | | When mapping the interrupts, the gpio_to_irq function did not consider the bank number of the gpio pin in question, only the offset or the interrupt number in the bank. As a result, requests for interrupts in the later banks get mapped to the first bank. This issue was discovered while enabling mmc on the new sun8i platform. The tablet I have uses a pin/interrupt from the second bank to do mmc card detection. Tested on this very device with register inspection and actual mmc card insertion/removal. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Define enable / disable irq callbacksHans de Goede2014-07-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers use disable_irq / enable_irq and do the work clearing the source in another thread instead of using a threaded interrupt handler. The irqchip used not having irq_disable and irq_enable callbacks in this case, will lead to unnecessary spurious interrupts: On a disable_irq in a chip without a handler for this, the irq core will remember the disable, but not actually call into the irqchip. With a level triggered interrupt (where the source has not been cleared) this will lead to an immediate retrigger, at which point the irq-core will mask the irq. So having an irq_disable callback in the irqchip will save us the interrupt firing a 2nd time for nothing. Drivers using disable / enable_irq like this, will call enable_irq when they finally have cleared the interrupt source, without an enable_irq callback, this will turn into an unmask, at which point the irq will trigger immediately because when it was originally acked the level was still high, so the ack was a nop. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Properly handle level triggered gpio interruptsHans de Goede2014-07-111-8/+31
| | | | | | | | | | | | For level triggered gpio interrupts we need to use handle_fasteoi_irq, like we do with the irq-sunxi-nmi driver. This is necessary to give threaded interrupt handlers a chance to actuall clear the source of the interrupt (which may involve sleeping waiting for i2c / spi / mmc transfers), before acknowledging the interrupt. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Move setting of mux to irq typeHans de Goede2014-07-111-8/+16
| | | | | | | | | | With level triggered interrupt mask / unmask will get called for each interrupt, doing the somewhat expensive mux setting on each unmask thus is not a good idea. Instead add a request_resources callback and do it there. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add IRQCHIP_SKIP_SET_WAKE flag for pinctrl irq chipChen-Yu Tsai2014-07-111-0/+1
| | | | | | | | | | | The sunxi pinctrl irq chip driver does not support wakeup at the moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers using wakeup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Add HSCIF pin supportNobuhiro Iwamatsu2014-07-111-0/+250
| | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONFUwe Kleine-König2014-07-111-2/+2
| | | | | | | | | | These symbols are supposed to be selected by the drivers actually needing them. The only situation where it would make sense to enable them without a driver selecting them is when an out-of-tree pinctrl driver is used or for compile testing. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: spear: switch plgpio to irqchip helpersLinus Walleij2014-06-192-51/+31
| | | | | | | | | | | | | | This switches the SPEAr PLGPIO driver over to using the irqchip helpers. As part of this effort, also get rid of the strange irq_base calculation and failure to use d->hwirq for obtaining a local irqchip offset. Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: spear-devel@list.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Implement multiple interrupt banks supportMaxime Ripard2014-06-192-23/+76
| | | | | | | | | The A23 and A31 support multiple interrupt banks. Support it by adding a linear domain covering all the banks. It's trickier than it should because there's an interrupt per bank, so we have multiple interrupts using the same domain. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Declare the interrupt function for the A31Maxime Ripard2014-06-191-72/+144
| | | | | | | | | The primary pinctrl device has 4 interrupt banks. As usual, to be able to generate interrupts, the pins supporting it need to be muxed to a special function. Declare these functions in the pins array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Declare the number of interrupt banks in the descriptorMaxime Ripard2014-06-197-0/+7
| | | | | | | | Declare in the description structure associated to the compatible the number of interrupt banks the device has. For now, we're not doing anything with it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add macro definition for pinctrl with more than one interruptMaxime Ripard2014-06-191-0/+9
| | | | | | | | | | | | The A31 and A23, unlike the other Allwinner SoCs, have several interrupts banks and parent interrupts, while the other only have up to 32 interrupts in a single bank and a single parent interrupt. Start supporting it by introducing a function macro to declare irq functions and their banks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Remove irq_mask_ack and use irq_ack insteadMaxime Ripard2014-06-191-14/+2
| | | | | | | | | If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask, just declare irq_ack. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.16-1' of ↵Linus Torvalds2014-06-0356-6179/+10510
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
| * pinctrl: sirf: fix a bad conflict resolutionLinus Walleij2014-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | Commit 294d1351ff47726f0f110b88e816cbafe89512fb "pinctrl: sirf: switch to using allocated state container" caused a build conflict due to a bad conflict resolution when cherry-picking the patch. Fix it up. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add more MSM8X74 pin definitionsAndy Gross2014-05-291-139/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pin definitiones for the MSM8x74 TLMM. New definitions include: BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins. Signed-off-by: Andy Gross <agross@codeaurora.org> Acked-By: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: ipq8064: Fix naming conventionKumar Gala2014-05-291-1/+1
| | | | | | | | | | | | | | | | Drop underscore in spdif_groups to match all other groups. Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add missing sdc1 and sdc3 groupsBjorn Andersson2014-05-281-0/+47
| | | | | | | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sirf: switch to using allocated state containerLinus Walleij2014-05-281-93/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | This rewrites the SIRF pinctrl driver to allocate a state container for the GPIO chip, just as is done for the pin controller, and use the gpiochip_add_pin_range() to add the range from the gpiochip side rather than adding the range from the pinctrl side. All resulting changes are done in order to pass around a state container rather than refer to a static global object. Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Enable "power-source" to be extracted from DT filesIvan T. Ivanov2014-05-281-0/+1
| | | | | | | | | | | | | | | | | | Add "power-source" property to generic options used for DT parsing files. This enables drivers, which use generic pin configurations, to get the value passed to this property. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: create irq/pin mapping during initChen-Yu Tsai2014-05-271-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq/pin mapping is used to lookup the pin to mux to the irq function when the irq is enabled. It is created when gpio_to_irq is called. Creating the mapping during init allows us to map the interrupts directly from the device tree. Originally the IRQ to pin mapping was created when gpio_to_irq was called with a GPIO handle. The mapping in turn is used to mux the pin into EINT mode. If the mapping is created during gpio_to_irq, we can't use the interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>". Instead we'd have to use "gpios = <&pio A B>", then pass the gpio through to gpio_to_irq. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpyBenoit Taine2014-05-271-2/+1
| | | | | | | | | | | | | | | | This issue was reported by coccicheck using the semantic patch at scripts/coccinelle/api/memdup.cocci Signed-off-by: Benoit Taine <benoit.taine@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: berlin: Use devm_ioremap_resource()Jingoo Han2014-05-273-9/+9
| | | | | | | | | | | | | | | | | | Use devm_ioremap_resource() because devm_request_and_ioremap() is obsoleted by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sirf: fix typo for GPIO bank numberBarry Song2014-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The patch 7420d2d09b12: "pinctrl: sirf: switch driver to use gpiolib irqchip helpers" from Apr 15, 2014, leads to the following static checker warning: drivers/pinctrl/sirf/pinctrl-sirf.c:578 sirfsoc_gpio_handle_irq() warn: buffer overflow 'sgpio_chip.sgpio_bank' 5 <= 31 Cc: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: depend on RESET_CONTROLLERMaxime Ripard2014-05-271-0/+1
| | | | | | | | | | | | | | | | | | The A31 R_PIO driver depends on the reset framework in a mandatory way. Express this by adding a depends on the reset framework in Kconfig Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: fix pin numbers passed to register offset helpersChen-Yu Tsai2014-05-271-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses. This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add pinctrl driver for imx6sxAnson Huang2014-05-273-0/+415
| | | | | | | | | | | | | | | | | | Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occursAlexander Stein2014-05-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip) gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The associated GPIO chip for the IRQ chip is overwritten each time, because they share the same hard IRQ line. Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will not be cleared, retriggering the ISR. Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip and walk the list in the irq handler. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: switch to using generic GPIO irqchip helpersLinus Walleij2014-05-232-72/+28
| | | | | | | | | | | | | | | | | | | | This switches the Qualcomm MSM pin control driver over to using the generic GPIO irqchip helpers. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Fix multiple registration issueMaxime Ripard2014-05-231-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the support for the PRCM muxer on the A31 has been added, the global static pinctl_desc definition has been left as is. Unfortunately, this structure is used to register the pinctrl device, and prior to this registration, we set the name and pins field. Since this structure is shared across instances, that means that the latest registered pinctrl device wins in setting the name, pins and pins numbers, which is not really a good thing. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Fix recursive dependencyMaxime Ripard2014-05-232-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following configuration error: drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected! drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10 drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI one. We still need to keep PINCTRL_SUNXI at the moment in order to preserve bisectability. Indeed, during that merge window, we also introduced the MACH_SUN* symbols. Since it's going through different trees, we can't rely on the fact that the options will be there, while ARCH_SUNXI still select PINCTRL_SUNXI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-31 06:55:04 +0100