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* pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chipVenkata Narendra Kumar Gutta2020-05-121-0/+25
| | | | | | | | | | | | | | | Wakeup capable GPIO IRQs routed via PDC are not being migrated when a CPU is hotplugged. Add affinity callbacks to msmgpio IRQ chip to update the affinity of wakeup capable IRQs. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> [mkshah: updated commit text and minor code fixes] Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1588314617-4556-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'intel-pinctrl-v5.7-2' of ↵Linus Walleij2020-04-173-7/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.7-2 * Enable pin configuration setting for Baytrail * Fix interrupt handling due to hardware sighting for Cherryview * Fix PAD lock offset for Sunrisepoint-H The following is an automated git shortlog grouped by driver: baytrail: - Enable pin configuration setting for GPIO chip cherryview: - Add missing spinlock usage in chv_gpio_irq_handler sunrisepoint: - Fix PAD lock register offset for SPT-H
| * pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handlerGrace Kao2020-04-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e. cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler") Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers") Signed-off-by: Grace Kao <grace.kao@intel.com> Reported-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * pinctrl: baytrail: Enable pin configuration setting for GPIO chipAndy Shevchenko2020-04-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | It appears that pin configuration for GPIO chip hasn't been enabled yet due to absence of ->set_config() callback. Enable it here for Intel Baytrail. Fixes: c501d0b149de ("pinctrl: baytrail: Add pin control operations") Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-HAndy Shevchenko2020-04-131-7/+8
| | | | | | | | | | | | | | | | | | It appears that SPT-H variant has different offset for PAD locking registers. Fix it here. Fixes: 551fa5801ef1 ("pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* | pinctrl: qcom: fix wrong write in update_dual_edgeAnsuel Smith2020-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix a typo in the readl/writel accessor conversion where val is used instead of pol changing the behavior of the original code. Cc: stable@vger.kernel.org Fixes: 6c73698904aa pinctrl: qcom: Introduce readl/writel accessors Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200414003726.25347-1-ansuelsmth@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: actions: fix function group name for i2c0_groupAmit Singh Tomar2020-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 6f87359e8bca ("pinctrl: actions: Fix functions groups names for S700 SoC") following error has been observed while booting Linux on Cubieboard7-lite(based on S700 SoC). [ 1.206245] pinctrl-s700 e01b0000.pinctrl: invalid group "i2c0_mfp" for function "i2c0" This commit fixes it by using correct name for i2c0_group. Fixes: 6f87359e8bca ("pinctrl: actions: Fix functions groups names for S700 SoC") Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Link: https://lore.kernel.org/r/1586757913-5438-1-git-send-email-amittomer25@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: remove shadow variable declarationLight Hsieh2020-04-161-2/+0
|/ | | | | | | | | Remove shadow declaration of variable 'pullup' in mtk_pinconf_get() Signed-off-by: Light Hsieh <light.hsieh@mediatek.com> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Link: https://lore.kernel.org/r/1586255632-27528-1-git-send-email-light.hsieh@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'gpio-v5.7-1' of ↵Linus Torvalds2020-04-042-5/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO development for the v5.7 kernel cycle. Core and userspace API: - The userspace API KFIFOs have been imoproved with locks that do not block interrupts. This makes us better at getting events to userspace without blocking or disturbing new events arriving in the same time. This was reviewed by the KFIFO maintainer Stefani. This is a generic improvement which paves the road for similar improvements in other subsystems. - We provide a new ioctl() for monitoring changes in the line information, such as when multiple clients are taking lines and giving them back, possibly reconfiguring them in the process: we can now monitor that and not get stuck with stale static information. - An example tool 'gpio-watch' is provided to showcase this functionality. - Timestamps for events are switched to ktime_get_ns() which is monotonic. We previously had a 'realtime' stamp which could move forward and *backward* in time, which probably would just cause silent bugs and weird behaviour. In the long run we see two relevant timestamps: ktime_get_ns() or the timestamp sometimes provided by the GPIO hardware itself, if that exists. - Device Tree overlay support for GPIO hogs. On systems that load overlays, these overlays can now contain hogs, and will then be respected. - Handle pin control interaction with nonexisting pin ranges in the GPIO library core instead of in the individual drivers. New drivers: - New driver for the Mellanox BlueField 2 GPIO controller. Driver improvements: - Introduce the BGPIOF_NO_SET_ON_INPUT flag to the generic MMIO GPIO library and use this flag in the MT7621 driver. - Texas Instruments OMAP CPU power management improvements, such as blocking of idle on pending GPIO interrupts" * tag 'gpio-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (59 commits) Revert "gpio: eic-sprd: Use devm_platform_ioremap_resource()" pinctrl: Unconditionally assign .request()/.free() gpio: Unconditionally assign .request()/.free() gpio: export of_pinctrl_get to modules pinctrl: Define of_pinctrl_get() dummy for !PINCTRL gpio: Rename variable in core APIs gpio: Avoid using pin ranges with !PINCTRL gpiolib: Remove unused gpio_chip parameter from gpio_set_bias() gpiolib: Pass gpio_desc to gpio_set_config() gpiolib: Introduce gpiod_set_config() tools: gpio: Fix out-of-tree build regression gpio: gpiolib: fix a doc warning gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 gpio: tegra186: Add support for pin ranges gpio: Support GPIO controllers without pin-ranges ARM: integrator: impd1: Use GPIO_LOOKUP() helper macro gpio: brcmstb: support gpio-line-names property tools: gpio: Fix typo in gpio-utils tools: gpio-hammer: Apply scripts/Lindent and retain good changes gpiolib: gpio_name_to_desc: factor out !name check ...
| * pinctrl: Unconditionally assign .request()/.free()Thierry Reding2020-04-021-5/+2
| | | | | | | | | | | | | | | | | | | | | | The gpiochip_generic_request() and gpiochip_generic_free() functions can now deal properly with chips that don't have any pin-ranges defined, so they can be assigned unconditionally. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200401200527.2982450-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * gpio: export of_pinctrl_get to modulesStephen Rothwell2020-04-011-0/+1
| | | | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Link: https://lore.kernel.org/r/20200401151904.6948af20@canb.auug.org.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v5.7-1' of ↵Linus Torvalds2020-04-0353-607/+2911
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.7 kernel cycle. There are no core changes this time, only driver developments: - New driver for the Dialog Semiconductor DA9062 Power Management Integrated Circuit (PMIC). - Renesas SH-PFC has improved consistency, with group and register checks in the configuration checker. - New subdriver for the Qualcomm IPQ6018. - Add the RGMII pin control functionality to Qualcomm IPQ8064. - Performance and code quality cleanups in the Mediatek driver. - Improve the Broadcom BCM2835 support to cover all the GPIOs that exist in it. - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on suspend. - Add some missing groups and functions to the Ingenic driver. - Convert some of the Freescale device tree bindings to use the new and all improved JSON YAML markup. - Refactorings and support for the SFIO/GPIO in the Tegra194 SoC driver. - Support high impedance mode in the Spreadtrum/Unisoc driver" * tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits) pinctrl: qcom: fix compilation error pinctrl: qcom: use scm_call to route GPIO irq to Apps pinctrl: sprd: Add pin high impedance mode support pinctrl: sprd: Use the correct pin output configuration pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 pinctrl: tegra: Renumber the GG.0 and GG.1 pins pinctrl: tegra: Do not add default pin range on Tegra194 pinctrl: tegra: Pass struct tegra_pmx for pin range check pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo pinctrl: tegra: Fix whitespace issues for improved readability pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow pinctrl: freescale: drop the dependency on ARM64 for i.MX8M Revert "pinctrl: mvebu: armada-37xx: use use platform api" dt-bindings: pinctrl: at91: Fix a typo ("descibe") pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm pinctrl: sprd: Fix the kconfig warning pinctrl: ingenic: add hdmi-ddc pin control group pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member pinctrl: sprd: Allow the SPRD pinctrl driver building into a module pinctrl: Export some needed symbols at module load time ...
| * | pinctrl: qcom: fix compilation errorAnsuel Smith2020-03-311-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pinctrl: qcom: use scm_call to route GPIO irq to Apps has a typo in the patch and introduced a compilation error. Fixes: 13bec8d4 pinctrl: qcom: use scm_call to route GPIO irq to Apps Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20200331134603.13513-1-ansuelsmth@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: use scm_call to route GPIO irq to AppsAjay Kishore2020-03-281-6/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed. Signed-off-by: Ajay Kishore <akisho@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sprd: Add pin high impedance mode supportLinhua Xu2020-03-271-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Spreadtrum pin controller, it will be the high impedance mode if disable input and output mode for a pin. Thus add PIN_CONFIG_BIAS_HIGH_IMPEDANCE configuration to support it. Signed-off-by: Linhua Xu <linhua.xu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/3bdac4c2673b54c940e511f3fa569ee33b87b8d5.1585124562.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sprd: Use the correct pin output configurationLinhua Xu2020-03-271-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Spreadtrum pin controller did not supply registers to set high level or low level for output mode, instead we should let the pin controller current configuration drive values on the line. So we should use the PIN_CONFIG_OUTPUT_ENABLE configuration to enable or disable the output mode. [Baolin Wang changes the commit message] Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Linhua Xu <linhua.xu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/8a6f91b49c17beb218e46b23084f59a7c7260f86.1585124562.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Add SFIO/GPIO programming on Tegra194Thierry Reding2020-03-273-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Renumber the GG.0 and GG.1 pinsThierry Reding2020-03-271-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Do not add default pin range on Tegra194Thierry Reding2020-03-272-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra194, almost all of the pin control programming happens in early boot firmware, so there is no use in having a pin range defined for all the pins. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Pass struct tegra_pmx for pin range checkThierry Reding2020-03-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass the struct tegra_pmx when checking for the pin range in device tree. This makes the call site a bit easier to read and will help keep that readability in a subsequent patch. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-7-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typoThierry Reding2020-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Properly spell "Schmitt" in the kerneldoc for pin group definitions. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: tegra: Fix whitespace issues for improved readabilityThierry Reding2020-03-271-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a few whitespace inconsistencies to make the code easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-5-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflowTakashi Iwai2020-03-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by: Takashi Iwai <tiwai@suse.de> Link: https://lore.kernel.org/r/20200311090644.20287-1-tiwai@suse.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: freescale: drop the dependency on ARM64 for i.MX8MPeng Fan2020-03-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving to support aarch32 mode on aarch64 hardware, need to drop the dependency on ARM64 to make the driver could be selected for ARM32. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1584070036-26447-2-git-send-email-peng.fan@nxp.com Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Revert "pinctrl: mvebu: armada-37xx: use use platform api"Linus Walleij2020-03-261-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 06e26b75f5e613b400116fdb7ff6206a681ab271. According to discussions, it causes a regression. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxmIgor Vavro2020-03-122-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the tsin pinctrl definitions needed for integrated DVB hardware support on Meson GXBB/GXL/GXM boards. changes in v2 - fix ordering and numbering of uart_c ping flagged by Otto in [1] [1] http://lists.infradead.org/pipermail/linux-amlogic/2020-March/015906.html Signed-off-by: Igor Vavro <afl2001@gmail.com> [updated commit message] Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/1583377666-13378-1-git-send-email-christianshewitt@gmail.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sprd: Fix the kconfig warningBaolin Wang2020-03-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On X86 plaform, if the CONFIG_OF is not selected, and set the CONFIG_SPRD_SC9860 as 'm', that will cause below waring: WARNING: unmet direct dependencies detected for PINCTRL_SPRD Depends on [n]: PINCTRL [=y] && OF [=n] && (ARCH_SPRD || COMPILE_TEST [=y]) Selected by [m]: - PINCTRL_SPRD_SC9860 [=m] && PINCTRL [=y] Thus move the configuration dependency under CONFIG_PINCTRL_SPRD_SC9860 to fix the warning. Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/eeb12d7843fb06f80e19f98eb25711231c3b610f.1583205650.git.baolin.wang7@gmail.com Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: add hdmi-ddc pin control groupPaul Boddie2020-03-021-0/+7
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/r/010d6ad3473fb4b1f1041888a071796180cdd838.1582913973.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sirf/atlas7: Replace zero-length array with flexible-array memberGustavo A. R. Silva2020-02-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Link: https://lore.kernel.org/r/20200227185837.GA4469@embeddedor Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sprd: Allow the SPRD pinctrl driver building into a moduleBaolin Wang2020-02-292-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change the config to 'tristate' and export some symbols needed by modules to allow the Spreadtrum pinctrl driver building into a module. Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/d7239f3c7379e402f665fc8927f635ac56691380.1582776447.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: Export some needed symbols at module load timeBaolin Wang2020-02-292-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Export the pin_get_name()/pinconf_generic_parse_dt_config() symbols needed by the Spreadtrum pinctrl driver when building it as a module. Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/f4e7e20afacb23e6fa7a6b33ea4319b2b3492840.1582776447.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: da9062: Fix error gpiolib.h pathYueHaibing2020-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc 7.4.0 build fails: drivers/pinctrl/pinctrl-da9062.c:28:10: fatal error: ../gpio/gpiolib.h: No such file or directory #include <../gpio/gpiolib.h> ^~~~~~~~~~~~~~~~~~~ Fix this wrong include path. Fixes: 56cc3af4e8c8 ("pinctrl: da9062: add driver support") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200228063429.47528-1-yuehaibing@huawei.com Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v5.7-tag1' of ↵Linus Walleij2020-02-263-68/+248
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.7 - Improve checks for pinctrl table validation, - Miscellaneous cleanups.
| | * | pinctrl: sh-pfc: Remove use of ARCH_R8A7795Geert Uytterhoeven2020-02-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951 in commit b925adfceb529389 ("soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200218112557.5924-1-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: gpio: Return early in gpio_pin_to_irq()Geert Uytterhoeven2020-02-211-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 4adeabd042422cee ("pinctrl: sh-pfc: Remove hardcoded IRQ numbers"), only a single operation needs to be performed after finding the wanted pin. Hence decrease the needed attention span of the casual reader by replacing the goto by a direct return. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200212090200.11106-1-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add function GPIO checksGeert Uytterhoeven2020-02-211-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for legacy function GPIO descriptors: 1. Function GPIOs must have a name, 2. Names must be unique, 3. Enum ID values must be unique. This exposes bugs like those fixed in - commit 884caadad128efad ("pinctrl: sh-pfc: sh7734: Fix duplicate TCLK1_B"), - commit 55b1cb1f03ad5eea ("pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs"), - commit 02aeb2f21530c98f ("pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs"), - commit db9c07272c8245a2 ("sh: sh7264: Remove bogus SSU GPIO function definitions"), - commit b4fba344a2930769 ("sh: sh7269: Remove bogus SSU GPIO function definitions"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-14-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add data register checksGeert Uytterhoeven2020-02-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for data register descriptors: 1. Register addresses must be unique. 2. Enum ID values must be unique. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-13-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add ioctrl register checksGeert Uytterhoeven2020-02-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for generic control register descriptors: 1. Register addresses must be unique. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-12-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add bias register checksGeert Uytterhoeven2020-02-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for bias register descriptors: 1. Pull-up and optional pull-down register addresses must be unique, 2. Referred pins must exist. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-11-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add drive strength register checksGeert Uytterhoeven2020-02-211-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add checks for drive strength register descriptors: 1. Register addresses must be unique, 2. Register fields must be non-overlapping, 3. Referred pins must exist. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-10-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Improve pin group checksGeert Uytterhoeven2020-02-211-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the checks for pin group descriptors: 1. Introduce a local variable for the current group, to make the checks easier to read, 2. Pin group names must be unique. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-9-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Improve pin function checksGeert Uytterhoeven2020-02-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the checks for pin function descriptors: 1. Merge declaration and assignment of the local variable for the current pin function, 2. Pin function names must be unique. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-8-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Improve pin checksGeert Uytterhoeven2020-02-211-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the checks for pin descriptors: 1. Introduce local variables for the current pin, to make the checks easier to read, 2. Pins must have a name, 3. Fix double printing of identical pin names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-7-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add check for enum ID conflictsGeert Uytterhoeven2020-02-211-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper to verify that enum IDs are unique, and use it to validate the enum ID arrays in config register descriptors. This exposes bugs like those fixed in: - commit 805f635703b2562b ("pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B"), - commit 884caadad128efad ("pinctrl: sh-pfc: sh7734: Fix duplicate TCLK1_B"), - commit 2a069a92811fb35b ("pinctrl: sh-pfc: sh7264: Fix Port K I/O Register 0 definition"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-6-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add check for config register conflictsGeert Uytterhoeven2020-02-211-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper to verify that register addresses are unique, and use it to validate config register descriptors. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-5-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add helper for safe name comparisonGeert Uytterhoeven2020-02-211-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper to check if two strings are identical, skipping NULL pointers. This simplifies callers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-4-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Add helpers for reportingGeert Uytterhoeven2020-02-211-52/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add helpers to report errors and warnings, and to increase the corresponding counters. This simplifies callers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-3-geert+renesas@glider.be
| | * | pinctrl: sh-pfc: checker: Move data before codeGeert Uytterhoeven2020-02-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restructure the checker to move all data definitions to the top, before the code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200110131927.1029-2-geert+renesas@glider.be
| * | | pinctrl: mediatek: Fix some off by one bugsDan Carpenter2020-02-211-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These comparisons should be >= instead of > to prevent accessing one element beyond the end of the hw->soc->pins[] array. Fixes: 3de7deefce69 ("pinctrl: mediatek: Check gpio pin number and use binary search in mtk_hw_pin_field_lookup()") Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20200218055247.74s2xa7veqx2do34@kili.mountain Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ingenic: Improve unreachable code generationJosh Poimboeuf2020-02-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the second loop of ingenic_pinconf_set(), it annotates the switch default case as unreachable(). The annotation is technically correct, because that same case would have resulted in an early function return in the previous loop. However, the compiled code is suboptimal. GCC seems to work extra hard to ensure that the unreachable code path triggers undefined behavior. The function would fall through to start executing whatever function happens to be next in the compilation unit. This is problematic because: a) it adds unnecessary 'ensure undefined behavior' logic, and corresponding i-cache footprint; and b) it's less robust -- if a bug were to be introduced, falling through to the next function would be catastrophic. Yet another issue is that, while objtool normally understands unreachable() annotations, there's one special case where it doesn't: when the annotation occurs immediately after a 'ret' instruction. That happens to be the case here because unreachable() is immediately before the return. Remove the unreachable() annotation and replace it with a comment. This simplifies the code generation and changes the unreachable error path to just silently return instead of corrupting execution. This fixes the following objtool warning: drivers/pinctrl/pinctrl-ingenic.o: warning: objtool: ingenic_pinconf_set() falls through to next function ingenic_pinconf_group_set() Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lore.kernel.org/r/bc20fdbcb826512cf76b7dfd0972740875931b19.1582212881.git.jpoimboe@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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