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* Revert "ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs"Rafael J. Wysocki2014-01-181-1/+0
| | | | | | | | | | | This reverts commit f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs), because it causes the Alan Cox' ASUS T100TA to "crash and burn" during boot if the Baytrail pinctrl driver is compiled in. Fixes: f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs) Reported-by: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Requested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
*-. Merge branches 'powercap' and 'acpi-lpss' with new device IDsRafael J. Wysocki2013-12-271-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | * powercap: powercap / RAPL: add support for ValleyView Soc * acpi-lpss: ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs
| | * ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDsPaul Drews2013-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the new ACPI ID (INT33FC) for the BayTrail GPIO banks as seen on a BayTrail M System-On-Chip platform. This ACPI ID is used by the BayTrail GPIO (pinctrl) driver to manage the Low Power Subsystem (LPSS). Signed-off-by: Paul Drews <paul.drews@intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | sh-pfc: Fix PINMUX_GPIO macroLaurent Pinchart2013-12-101-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | Commit 7cbb0e55e27e ("sh-pfc: Don't duplicate argument to PINMUX_GPIO macro") erronesouly modified the PINMUX_GPIO macro in a way that resulted in all pins being named "name". Fix the macro to name the pins correctly. Cc: stable@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | sh-pfc: sh7372: Fix pin bias setupLaurent Pinchart2013-12-031-1/+1
| | | | | | | | | | | | | | | | | | When computing the pin configuration register offset the bias setup code erroneously compares the pin number range with the loop index instead of the pin number. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | sh-pfc: r8a7740: Fix pin bias setupLaurent Pinchart2013-12-031-1/+1
| | | | | | | | | | | | | | | | | | When computing the pin configuration register offset the bias setup code erroneously compares the pin number range with the loop index instead of the pin number. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: Fix header file include guardAxel Lin2013-12-021-1/+1
| | | | | | | | | | | | | | Fix a trivial typo. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: missing unlock on error in rockchip_set_pull()Dan Carpenter2013-11-251-0/+1
| | | | | | | | | | | | | | | | | | | | We need to unlock here before returning -EINVAL. Fixes: 6ca5274d1d12 ('pinctrl: rockchip: add rk3188 specifics') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: fix some more bitwise AND testsDan Carpenter2013-11-251-3/+3
| | | | | | | | | | | | | | | | I sent a patch to fix some bitwise AND tests but I guess I missed some. Sorry about that. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: testing the wrong variableDan Carpenter2013-11-251-2/+2
|/ | | | | | | | | There is a copy and paste bug so we test "info->reg_base" instead of "info->reg_pull". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: single: call pcs_soc->rearm() whenever IRQ mask is changedRoger Quadros2013-11-141-7/+3
| | | | | | | | | | | | | | | | | | On OMAPs the IO ring must be rearmed each time the pad wakeup configuration is changed. So call pcs_soc->rearm() from pcs_irq_set(). As pinctrl-single is now an interrupt controller in some cases, we should follow the standards and keep the interrupts enabled constantly, and not just for wake-up events. The tracking of runtime vs wake-up interrupts can be handled separately for the automated runtime PM solution when we have it in the future. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> [tony@atomide.com: removed wrong comment, updated description] Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge tag 'gpio-v3.13-1' of ↵Linus Torvalds2013-11-122-0/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO changes from Linus Walleij: "Here is the bulk of GPIO changes for the v3.13 development cycle. I've got ACKs for the things that affect other subsystems (or it's my own subsystem, like pinctrl). Most of that pertain to an attempt from my side to consolidate and get rid of custom GPIO implementations in the ARM tree. I will continue doing this. The main change this time is the new GPIO descriptor API, background for this can be found in Corbet's summary from this january in LWN: http://lwn.net/Articles/533632/ Summary: - Merged the GPIO descriptor API from Alexandre Courbot. This is a first step toward trying to get rid of the global GPIO numberspace for the future. - Add an API so that driver can flag that a certain GPIO line is being used by a irqchip backend for generating IRQs, so that we can enforce checks, like not allowing users to switch that line to an output at runtime, since this makes no sense. Implemented corresponding calls in a few select drivers. - ACPI GPIO cleanups, refactorings and switch to using the descriptor-based interface. - Support for the TPS80036 Palmas GPIO variant. - A new driver for the Broadcom Kona GPIO SoC IP block. - Device tree support for the PCF857x driver. - A set of ARM GPIO refactorings with the goal of getting rid of a bunch of custom GPIO implementations from the arch/arm/* tree: * Move the IOP GPIO driver to the GPIO subsystem and fix all users to use the gpiolib API for accessing GPIOs. Delete the old custom GPIO implementation. * Delete the unused custom PXA GPIO implemention. * Convert all users of the IXP4 custom GPIO implementation to use gpiolib and delete the custom implementation. * Delete the custom Gemini GPIO implementation, also completely unused. - Various cleanups and renamings" * tag 'gpio-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (85 commits) gpio: gpio-mxs: Remove unneeded dt checks gpio: pl061: don't depend on CONFIG_ARM gpio: bcm-kona: add missing .owner to struct gpio_chip gpiolib: provide a declaration of seq_file in gpio/driver.h gpiolib: include gpio/consumer.h in of_gpio.h for desc_to_gpio() gpio: provide stubs for devres gpio functions gpiolib: devres: add missing headers gpiolib: make GPIO_DEVRES depend on GPIOLIB gpiolib: devres: fix devm_gpiod_get_index() gpiolib / ACPI: document the GPIO descriptor based interface gpiolib / ACPI: allow passing GPIOF_ACTIVE_LOW for GpioInt resources gpiolib / ACPI: add ACPI support for gpiod_get_index() gpiolib / ACPI: convert to gpiod interfaces gpiolib: add gpiod_get() and gpiod_put() functions gpiolib: port of_ functions to use gpiod gpiolib: export descriptor-based GPIO interface Fixup "MAINTAINERS: GPIO-INTEL-MID: add maintainer" gpio: bcm281xx: Don't print addresses of GPIO area in probe() gpio: tegra: use new gpio_lock_as_irq() API gpio: rcar: Include linux/of.h header ...
| * Merge tag 'v3.12-rc4' into develLinus Walleij2013-10-164-13/+13
| |\ | | | | | | | | | Linux 3.12-rc4
| * | pinctrl: coh901: mark GPIO lines used for IRQLinus Walleij2013-10-161-0/+5
| | | | | | | | | | | | | | | | | | | | | When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: mark GPIO lines used for IRQLinus Walleij2013-10-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'pinctrl-for-v3.13-1' of ↵Linus Torvalds2013-11-1243-124/+10532
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Main pin control pull request for the v3.13 cycle. The changes hitting arch/blackfin are ACKed by the Blackfin maintainer, and the device tree bindings are ACKed to the extent possible by someone from the device tree maintainers group. - Blackfin ADI pin control driver, we move yet another architecture under this subsystem umbrella. - Incremental updates to the Renesas Super-H PFC pin control driver. New subdriver for the r8a7791 SoC. - Non-linear GPIO ranges from the gpiolib side of things, this enabled simplified device tree bindings by referring entire groups of pins on some pin controller to act as back-end for a certain GPIO-chip driver. - Add the Abilis TB10x pin control driver used on the ARC architecture. Also the corresponding GPIO driver is merged through this tree, so the ARC has full support for pins and GPIOs after this. - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller instances. The i.MX1 and i.MX27 is an entirely new family (silicon) of controllers whereas i.MX50 is a variant of the previous supported controller. - Then the usual slew of fixes, cleanups and incremental updates" The ARC DT changes are apparently still pending, that hopefully gets sorted out in a timely manner. * tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: imx50: add pinctrl support code for the IMX50 SoC pinctrl: at91: copy define to driver pinctrl: remove minor dead code pinctrl: imx: fix using pin->input_val wrongly pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe() gpio: tb10x: fix return value check in tb10x_gpio_probe() gpio: tb10x: use module_platform_driver to simplify the code pinctrl: imx27: imx27 pincontrol driver pinctrl: imx1 core driver pinctrl: sh-pfc: r8a7791 PFC support sh-pfc: r8a7778: Add CAN pin groups gpio: add TB10x GPIO driver pinctrl: at91: correct a few typos pinctrl: mvebu: remove redundant of_match_ptr pinctrl: tb10x: use module_platform_driver to simplify the code pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe() pinctrl: add documentation for pinctrl_get_group_pins() pinctrl: rockchip: emulate both edge triggered interrupts pinctrl: rockchip: add rk3188 specifics pinctrl: rockchip: remove redundant check ...
| * | | pinctrl: imx50: add pinctrl support code for the IMX50 SoCGreg Ungerer2013-11-063-0/+435
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to support the specific pin arrangements of the Freescale IMX50 SoC. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: copy define to driverLinus Walleij2013-11-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The #define for the maximum number of GPIO blocks was retrieved into pinctrl-at91.c by implicit inclusion of <mach/gpio.h> from <linux/gpio.h> creating a dependency on machine-local <mach/gpio.h>. Break the depenency by copying this single define into the driver. Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: remove minor dead codeMichael Opdenacker2013-11-041-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes a test whether the 'desc' variable is NULL. This possibility has already been eliminated by the below test earlier in the loop: if (desc == NULL) { dev_warn(pctldev->dev, "could not get pin desc for pin %d\n", pins[i]); continue; } Found with Coverity: CID #1090078 Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: imx: fix using pin->input_val wronglyPeter Chen2013-11-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit: "pinctrl: imx: Use struct type for pins" relaced pin->input_reg by pin->input_val wrongly, fix it at this commit. Signed-off-by: Peter Chen <peter.chen@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge branch 'pinmux/next/pfc' of git://linuxtv.org/pinchartl/fbdev into develLinus Walleij2013-11-046-0/+4285
| |\ \ \
| | * | | pinctrl: sh-pfc: r8a7791 PFC supportHisashi Nakamura2013-10-275-0/+4230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PFC support for the r8a7791 SoC V2 including pin groups for on-chip devices such as MSIOF, SCIF, USB, MMC, SDHI, DU. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> Signed-off-by: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com> Signed-off-by: Nobuyuki HIRAI <nobuyuki.hirai.xe@renesas.com> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [damm@opensource.se: Forward ported to upstream, minor fixes] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| | * | | sh-pfc: r8a7778: Add CAN pin groupsSergei Shtylyov2013-10-271-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CAN data and clock pin groups to R8A7778 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * | | | pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe()Wei Yongjun2013-11-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap_nocache() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: imx27: imx27 pincontrol driverMarkus Pargmann2013-10-293-0/+486
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx27 pincontrol driver using the imx1 core driver. The DT bindings are similar to other imx pincontrol drivers. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: imx1 core driverMarkus Pargmann2013-10-294-0/+732
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Core driver for register formats of imx1/imx21/imx27 processors. The pins of those processors are grouped into ports. Each port has 32 pins. The pins mux configuration is controlled by registers with 1 or 2 bit per pin, depending on the specific control register. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: at91: correct a few typosAlexandre Belloni2013-10-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mvebu: remove redundant of_match_ptrSachin Kamat2013-10-234-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data structure of_match_ptr() protects is always compiled in. Hence of_match_ptr() is not needed. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: tb10x: use module_platform_driver to simplify the codeWei Yongjun2013-10-231-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe()Wei Yongjun2013-10-231-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the error handling in tb10x_pinctrl_probe(): - devm_ioremap_resource() return ERR_PTR() and never return NULL - remove the dev_err call to avoid redundant error message - pinctrl_register() returns NULL not ERR_PTR() Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: emulate both edge triggered interruptsHeiko Stübner2013-10-161-7/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio interrupt controller on Rockchip socs can do edge triggers only for single edges but not both. Nevertheless a lot of gpio users rely on the availability of both-edge triggered interrupts - i.e. gpio-keys. Therefore implement a solution similar to pinctrl-coh901 re-setting the triggering edge depending on the gpio value in the interrupt demuxer. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: add rk3188 specificsHeiko Stübner2013-10-161-7/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Besides the pull registers sitting in a separate place, the rk3188 also has the peculiarity that the pull registers of the first bank are split and the first half is sitting in the register space of the pmu. Therefore this adds a special bank-type for the first bank, to handle the two register sources. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: remove redundant checkHeiko Stübner2013-10-161-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check limiting bias options to supported ones is already done thru rockchip_pinconf_pull_valid. Therefore this check is redundant and can be removed. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: add support for multiple bank typesHeiko Stübner2013-10-161-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are Rockchip SoCs, namely the rk3188, that combine a set of regular banks with banks that need special handling for some settings. Therefore add the possibility for the driver to handle more than one bank type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: separate different sub-types moreHeiko Stübner2013-10-161-48/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Further investigation of the different Rockchip SoCs showed that the differences especially in the pull settings are quite deep. As further patches will show, the register layout for the pulls of the rk3188 is quite strange. Also it is to assume, that later Rockchip SoCs may introduce even more quirks in this regard, making it hard to support all of those using the current generic pull_* variables. Therefore move the driver to hold the type of controller in an enum and do the handling according to it in the necessary places. Also instead of calculating the register in the get and set pull functions move it to a type-specific callback. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: dove: unset twsi option3 for gconfig as wellRoel Kluin2013-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a typo which left twsi config3 option enabled. Cc: stable@vger.kernel.org Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: add TB10x pin control driverChristian Ruppert2013-10-163-0/+891
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs. Used to control the pinmux and is a prerequisite for the GPIO driver. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl/gpio: non-linear GPIO ranges accesible from gpiolibChristian Ruppert2013-10-161-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the infrastructure required to register non-linear gpio ranges through gpiolib and the standard GPIO device tree bindings. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pincntrl: add support for ams AS3722 pin control driverLaxman Dewangan2013-10-103-0/+642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AS3722 is a compact system PMU suitable for mobile phones, tablets etc. Add a driver to support accessing the GPIO, pinmux and pin configuration of 8 GPIO pins found on the ams AS3722 through pin control driver and gpiolib. The driver will register itself as the pincontrol driver and gpio driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: pinctrl-adi2: disable IRQ when setting valueSonic Zhang2013-10-091-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO output value should be set after the GPIO interrupt is disabled. Use BIT macro as well. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> [Edited commit message] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: pinctrl-adi2: Remove nested lock+irqsave that resue flags.Sonic Zhang2013-10-091-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also avoid use NULL pointer in error message. v2-changes: - use port pinter only after checking Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: palmas: remove pin config BIAS_PULL_PIN_DEFAULT supportLaxman Dewangan2013-10-081-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Palmas devices do not support the default bias configuration and hence removing this option from valid pin config parameters. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'v3.12-rc4' into develLinus Walleij2013-10-082-8/+9
| |\ \ \ | | | |/ | | |/| | | | | Linux 3.12-rc4
| * | | pinctrl: sirf: add USB1/UART1 pinmux usb/uart shareRong Wang2013-10-084-6/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1). here we add this pinmux capability. USB1/UART1 mode selection has dedicated control register in RSC module, here we attach the register offset of private data of related pin groups. Signed-off-by: Rong Wang <Rong.Wang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sirf: add lost USP-based UART pin groups for prima2Qipan Li2013-10-081-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USP(Universal Serial Ports) can be UART as commit 5df831117b85a08e7aa, this patch defines the USP-based UART function pin groups for prima2. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sirf: add lost uart0-no-stream-control pingroup for prima2Qipan Li2013-10-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the old codes defined uart0_nostreamctrl_pins, but missed pingroup and padmux definition for it. this patch fixes it. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: remove redundant of_match_ptrSachin Kamat2013-10-0811-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data structure of_match_ptr() protects is always compiled in. Hence of_match_ptr() is not needed. This is a squash commit of: pinctrl: at91: Remove redundant of_match_ptr pinctrl: exynos5440: Remove redundant of_match_ptr pinctrl: imx35: Remove redundant of_match_ptr pinctrl: imx51: Remove redundant of_match_ptr pinctrl: imx53: Remove redundant of_match_ptr pinctrl: imx6dl: Remove redundant of_match_ptr pinctrl: imx6q: Remove redundant of_match_ptr pinctrl: samsung: Remove redundant of_match_ptr pinctrl: vf610: Remove redundant of_match_ptr pinctrl: imx6sl: Remove redundant of_match_ptr pinctrl: plgpio: Remove redundant of_match_ptr Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge branch 'pinmux/next' of git://linuxtv.org/pinchartl/fbdev into develLinus Walleij2013-09-274-5/+239
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| | * | | sh-pfc: r8a7790: add pin definitions for the I2C3 interfaceGuennadi Liakhovetski2013-09-271-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are four I2C interfaces on r8a7790, each of them can be connected to one of the two respective I2C controllers, e.g. interface #0 can be configured to work with I2C0 or with IIC0. Additionally some of those interfaces can also use one of several pin sets. Interface #3 is special, because it can be used in automatic mode for DVFS. It only has one set of pins available and those pins cannot be used for anything else, they also lack the GPIO function. This patch uses the sh-pfc ability to configure pins, not associated with GPIOs and adds support for I2C3 to the r8a7790 PFC set up. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| | * | | sh-pfc: r8a7790: Add I2C pin groups and functionsUlrich Hecht2013-09-241-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.) Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 17:34:10 +0100