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* Merge tag 'riscv-for-linus-5.12-mw0' of ↵Linus Torvalds2021-02-263-0/+999
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "A handful of new RISC-V related patches for this merge window: - A check to ensure drivers are properly using uaccess. This isn't manifesting with any of the drivers I'm currently using, but may catch errors in new drivers. - Some preliminary support for the FU740, along with the HiFive Unleashed it will appear on. - NUMA support for RISC-V, which involves making the arm64 code generic. - Support for kasan on the vmalloc region. - A handful of new drivers for the Kendryte K210, along with the DT plumbing required to boot on a handful of K210-based boards. - Support for allocating ASIDs. - Preliminary support for kernels larger than 128MiB. - Various other improvements to our KASAN support, including the utilization of huge pages when allocating the KASAN regions. We may have already found a bug with the KASAN_VMALLOC code, but it's passing my tests. There's a fix in the works, but that will probably miss the merge window. * tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits) riscv: Improve kasan population by using hugepages when possible riscv: Improve kasan population function riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization riscv: Improve kasan definitions riscv: Get rid of MAX_EARLY_MAPPING_SIZE soc: canaan: Sort the Makefile alphabetically riscv: Disable KSAN_SANITIZE for vDSO riscv: Remove unnecessary declaration riscv: Add Canaan Kendryte K210 SD card defconfig riscv: Update Canaan Kendryte K210 defconfig riscv: Add Kendryte KD233 board device tree riscv: Add SiPeed MAIXDUINO board device tree riscv: Add SiPeed MAIX GO board device tree riscv: Add SiPeed MAIX DOCK board device tree riscv: Add SiPeed MAIX BiT board device tree riscv: Update Canaan Kendryte K210 device tree dt-bindings: add resets property to dw-apb-timer dt-bindings: fix sifive gpio properties dt-bindings: update sifive uart compatible string dt-bindings: update sifive clint compatible string ...
| * pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driverDamien Le Moal2021-02-193-0/+999
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pinctrl-k210.c pinctrl driver for the Canaan Kendryte K210 field programmable IO array (FPIOA) to allow configuring the SoC pin functions. The K210 has 48 programmable pins which can take any of 256 possible functions. This patch is inspired from the k210 pinctrl driver for the u-boot project and contains many direct contributions from Sean Anderson. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC FPIOA DRIVER" with myself listed as maintainer for this driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* | Merge tag 'pinctrl-v5.12-1' of ↵Linus Torvalds2021-02-2366-13152/+8765
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.12 kernel. This time a calm set with no core changes. New drivers/subdrivers: - Renesas R8A7790A0 pin controller. - Allwinner H616 and H616-R pin controllers. - Qualcomm SM8350 and SC8180x pin controllers. Improvements: - Redo the DT bindings for Ralink RT2880. - A common Qualcomm TLMM DT binding in YAML. - Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX" * tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt dt-bindings: pinctrl: Group tuples in pin control properties pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" pinctrl: at91-pio4: add support for slew-rate dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: actions: Add depends on || COMPILE_TEST pinctrl: single: set function name when adding function pinctrl: qcom: Add sc8180x TLMM driver dt-bindings: pinctrl: qcom: Add sc8180x binding dt-bindings: pinctrl: qcom: Define common TLMM binding pinctrl: qcom: Add SM8350 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings pinctrl: samsung: use raw_spinlock for s3c64xx dt-bindings: mediatek: mt8192: Fix dt_binding_check warning pinctrl: qcom: spmi-mpp: Add PM8019 compatible pinctrl: pinmux: add function selector to pinmux-functions pinctrl: samsung: use raw_spinlock for locking pinctrl: clarify #pinctrl-cells for pinctrl-single,pins pinctrl: actions: Add the platform dependency to drivers ...
| * | pinctrl: mediatek: Fix trigger type setting follow for unexpected interruptHailong Fan2021-02-151-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When flipping the polarity will be generated interrupt under certain circumstances, but GPIO external signal has not changed. Then, mask the interrupt before polarity setting, and clear the unexpected interrupt after trigger type setting completed. Remove mtk_eint_flip_edge: because mtk_eint_unmask already calls it. Signed-off-by: Hailong Fan <hailong.fan@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Link: https://lore.kernel.org/r/20210125041753.2214-1-hailong.fan@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nuvoton: npcm7xx: Fix alignment of table header commentJonathan Neuschäfer2021-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make it so that each column label is in the column that it is supposed to refer to. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20210130162954.918803-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'"Claudiu Beznea2021-02-121-53/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl warning. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea2021-02-121-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAMA7G5 supports slew rate configuration. Adapt the driver for this. For output switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: actions: Add depends on || COMPILE_TESTLinus Walleij2021-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I happened to apply the v1 of the patch restriction the selection to ARM or ARM64, sorry for my sloppiness. Fixing up the mistake as I can't back the patch out now. Fixes: 5784921f7b6c ("pinctrl: actions: Add the platform dependency to drivers") Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: single: set function name when adding functionDrew Fustini2021-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pcs_add_function() fails to set the function name in struct pcs_function when adding a new function. As a result this line in pcs_set_mux(): dev_dbg(pcs->dev, "enabling %s function%i\n", func->name, fselector); prints "(null)" for the function: pinctrl-single 44e10800.pinmux: enabling (null) function0 pinctrl-single 44e10800.pinmux: enabling (null) function1 pinctrl-single 44e10800.pinmux: enabling (null) function2 pinctrl-single 44e10800.pinmux: enabling (null) function3 With this fix, the output is now: pinctrl-single 44e10800.pinmux: enabling pinmux-uart0-pins function0 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function1 pinctrl-single 44e10800.pinmux: enabling pinmux-i2c0-pins function2 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function3 Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Robert Nelson <robertcnelson@beagleboard.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210125203542.51513-1-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: Add sc8180x TLMM driverBjorn Andersson2021-02-123-0/+1634
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver for the sc8180x TLMM block. A noteworthy difference from previous TLMM blocks is that the registers for GPIO 177 through 189 are for some reason offset from the typical layout. Other than that the driver is same old... Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: Add SM8350 pinctrl driverVinod Koul2021-02-123-0/+1659
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds pincontrol driver for tlmm block found in SM8350 SoC This patch is based on initial code downstream by Raghavendra. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: samsung: use raw_spinlock for s3c64xxChanho Park2021-01-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt for pinctrl-s3c64xx. Below patch converted spinlock_t to raw_spinlock_t but it didn't convert the s3c64xx's spinlock. Fixes: 1f306ecbe0f6 ("pinctrl: samsung: use raw_spinlock for locking") Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20210127001631.91209-1-chanho61.park@samsung.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-mpp: Add PM8019 compatibleKonrad Dybcio2021-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | PM8019 provides 6 MPPs. Add a compatible to support them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210115171115.123155-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'intel-pinctrl-v5.12-1' of ↵Linus Walleij2021-01-263-34/+88
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.12-1 * Enable pin control on Intel Alder Lake-P * Traverse through capabilities, convert them to features for the future use The following is an automated git shortlog grouped by driver: intel: - Convert capability list to features - Drop unnecessary check for predefined features - Split intel_pinctrl_add_padgroups() for better maintenance tigerlake: - Add Alder Lake-P ACPI ID
| | * | pinctrl: tigerlake: Add Alder Lake-P ACPI IDAndy Shevchenko2021-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Alder Lake-P PCH has the same GPIO hardware than Tiger Lake-LP PCH but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Convert capability list to featuresAndy Shevchenko2021-01-082-3/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Communities can have features provided in the capability list. Traverse the list and convert to respective features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Drop unnecessary check for predefined featuresAndy Shevchenko2021-01-081-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | None of the drivers is overriding features. Remove unnecessary check. While here, rename rev to value to make easier further development. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Split intel_pinctrl_add_padgroups() for better maintenanceAndy Shevchenko2021-01-081-20/+40
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the intel_pinctrl_add_padgroups() is twisted a bit due to a different nature of the pin control hardware implementations. Thus, its maintenance is a bit hard. Besides that some pieces of code are run on all hardware and make this code slightly inefficient, and moreover, validation for one case is done in a wrong time in a flow which makes it even slower. Split intel_pinctrl_add_padgroups() to two functions, one per hardware implementation, for better maintenance and readability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * | pinctrl: pinmux: add function selector to pinmux-functionsDrew Fustini2021-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the function selector to the pinmux-functions debugfs output. This is an integer which is the index into the pinmux function tree. It will make it easier to correlate function name to function selector without having to count the lines in the output. Example output of "pinmux-functions": function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ] function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ] function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ] function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ] function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ] function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ] function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ] function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ] function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ] function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ] function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ] Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Robert Nelson <robertcnelson@beagleboard.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210123202212.528046-1-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: samsung: use raw_spinlock for lockingChanho Park2021-01-234-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt. This can avoid BUG() assertion when irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex which is preemptible when we apply preempt-rt patches. According to "Documentation/driver-api/gpio/driver.rst", "Realtime considerations: a realtime compliant GPIO driver should not use spinlock_t or any sleepable APIs (like PM runtime) as part of its irqchip implementation. - spinlock_t should be replaced with raw_spinlock_t.[1] " Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: actions: Add the platform dependency to driversManivannan Sadhasivam2021-01-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64 platforms. So let's add the correct platform dependency to avoid them being selected on the other. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210121062547.27173-1-manivannan.sadhasivam@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for the Allwinner H616-R pin controllerAndre Przywara2021-01-213-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for the Allwinner H616 pin controllerAndre Przywara2021-01-213-0/+554
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: Improve JZ4760 supportPaul Cercueil2021-01-211-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add otg function and otg-vbus group. - Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special groups. Change the lcd-24bit group so that it only selects the pins that aren't in the lcd-18bit and lcd-generic groups (which breaks Device Tree in theory, but there is none out there for any JZ4760 based board, yet). Remove the lcd-no-pins group which is just useless. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove ste u300 driverArnd Bergmann2021-01-213-1118/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove coh901 driverArnd Bergmann2021-01-214-791/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove sirf atlas/prima driversArnd Bergmann2021-01-218-9451/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove zte zx driverArnd Bergmann2021-01-217-1590/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: Simplify bool comparisonJiapeng Zhong2021-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the follow coccicheck warnings: ./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING: Comparison to bool. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com> Link: https://lore.kernel.org/r/1610705349-24310-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ingenic: Only support SoCs enabled in configPaul Cercueil2021-01-181-12/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves about 14 KiB, by allowing the compiler to garbage-collect all the functions and tables that correspond to SoCs that were disabled in the config. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'renesas-pinctrl-for-v5.12-tag1' of ↵Linus Walleij2021-01-186-17/+4531
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.12 - Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC.
| | * | pinctrl: renesas: r8a779a0: Add TPU pins, groups and functionsUlrich Hecht2021-01-141-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add TMU pins, groups and functionsUlrich Hecht2021-01-141-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functionsUlrich Hecht2021-01-141-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC driver. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add PWM pins, groups and functionsUlrich Hecht2021-01-141-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functionsUlrich Hecht2021-01-141-0/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add MMC pins, groups and functionsUlrich Hecht2021-01-141-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and functionUlrich Hecht2021-01-141-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functionsUlrich Hecht2021-01-141-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add DU pins, groups and functionUlrich Hecht2021-01-141-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functionsUlrich Hecht2021-01-141-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CANFD 0-7 and CANFD clock pinmux support for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functionsUlrich Hecht2021-01-141-0/+595
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and PTP pins for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add I2C pins, groups and functionsUlrich Hecht2021-01-141-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functionsUlrich Hecht2021-01-141-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: Initial R8A779A0 (V3U) PFC supportUlrich Hecht2021-01-145-0/+2529
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC, including bias, drive strength and voltage control. Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: Add PORT_GP_CFG_{2,31} macrosUlrich Hecht2021-01-141-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: Add I/O voltage level flagUlrich Hecht2021-01-142-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds config macros describing the voltage levels available on a pin. The current default (3.3V/1.8V) maps to zero to avoid having to change existing PFC implementations. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: Implement unlock register masksUlrich Hecht2021-01-142-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: checker: Restrict checks to Renesas platformsGeert Uytterhoeven2021-01-121-0/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin control driver runs sanity checks against the pin control tables. This may cause lots of output on the console, and can be annoying in ARM multi-platform kernels. Fix this by only running the checks when running on SuperH, or on a DT platform supported by the Renesas pin controller driver. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
| * | pinctrl: sprd: Simplify bool comparisonYANG LI2021-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following coccicheck warning: ./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to bool Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/1610440080-68600-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 19:47:42 +0100