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* pinctrl: qcom: spmi-gpio: Add PM/PMI8950 compatibilityAngeloGioacchino Del Regno2019-11-051-0/+3
| | | | | | | | | The PM8950 features 8 GPIOs with hole in 3 and PMI8950 has only two; these PMICs are totally compatible with this driver. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191031103507.30678-2-kholk11@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: bcm: nsp: implement get_directionChris Packham2019-11-041-0/+14
| | | | | | | | | | | The get_direction api is strongly recommended to be implemented. In fact if it is not implemented gpio-hogs will not get the correct direction. Add an implementation of get_direction for the nsp-gpio driver. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20191104001819.2300-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: bcm: nsp: use gpiolib infrastructure for interruptsChris Packham2019-11-041-63/+42
| | | | | | | | | | | | | | Use more of the gpiolib infrastructure for handling interrupts. The root interrupt still needs to be handled manually as it is shared with other peripherals on the SoC. This will allow multiple instances of this driver to be supported and will clean up gracefully on failure thanks to the device managed APIs. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20191104001819.2300-2-chris.packham@alliedtelesis.co.nz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: amd: fix __iomem annotation in amd_gpio_irq_handler()Ben Dooks (Codethink)2019-11-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | The regs pointer in amd_gpio_irq_handler() should have __iomem on it, so add that to fix the following sparse warnings: drivers/pinctrl/pinctrl-amd.c:555:14: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/pinctrl-amd.c:555:14: expected unsigned int [usertype] *regs drivers/pinctrl/pinctrl-amd.c:555:14: got void [noderef] <asn:2> *base drivers/pinctrl/pinctrl-amd.c:563:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-amd.c:563:34: expected void const volatile [noderef] <asn:2> *addr drivers/pinctrl/pinctrl-amd.c:563:34: got unsigned int [usertype] * drivers/pinctrl/pinctrl-amd.c:580:34: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/pinctrl-amd.c:580:34: expected void const volatile [noderef] <asn:2> *addr drivers/pinctrl/pinctrl-amd.c:580:34: got unsigned int [usertype] * drivers/pinctrl/pinctrl-amd.c:587:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/pinctrl-amd.c:587:25: expected void volatile [noderef] <asn:2> *addr drivers/pinctrl/pinctrl-amd.c:587:25: got unsigned int [usertype] * Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20191022151154.5986-1-ben.dooks@codethink.co.uk Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: sc7180: Add missing tile info in SDC_QDSD_PINGROUP/UFS_RESETRajendra Nayak2019-11-041-8/+10
| | | | | | | | | | | | | | The SDC_QDSD_PINGROUP/UFS_RESET macros are missing the .tile info needed to calculate the right register offsets. Adding them here and also adjusting the offsets accordingly. Fixes: f2ae04c45b1a ("pinctrl: qcom: Add SC7180 pinctrl driver") Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/20191021141507.24066-1-rnayak@codeaurora.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: Enable slewrate by default on SAM9X60Codrin Ciubotariu2019-11-031-2/+2
| | | | | | | | | | | | | | | | | | On SAM9X60, slewrate should be enabled on pins with a switching frequency below 50Mhz. Since most of our pins do not exceed this value, we enable slewrate by default. Pins with a switching value that exceeds 50Mhz will have to explicitly disable slewrate. This patch changes the ABI. However, the slewrate macros are only used by SAM9X60 and, at this moment, there are no device-tree files available for this platform. Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'sh-pfc-for-v5.5-tag2' of ↵Linus Walleij2019-11-036-21/+56
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.5 (take two) - Add support for the new R-Car M3-W+ (r8a77961) SoC, - Small fixes and cleanups.
| * pinctrl: sh-pfc: sh7734: Fix duplicate TCLK1_BGeert Uytterhoeven2019-11-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions for bit field [19:18] of the Peripheral Function Select Register 3 were accidentally copied from bit field [20], leading to duplicates for the TCLK1_B function, and missing TCLK0, CAN_CLK_B, and ET0_ETXD4 functions. Fix this by adding the missing GPIO_FN_CAN_CLK_B and GPIO_FN_ET0_ETXD4 enum values, and correcting the functions. Reported-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191024131308.16659-1-geert+renesas@glider.be
| * pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC supportGeert Uytterhoeven2019-11-015-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Pin Function Controller in the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is pin compatible with R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122955.12420-4-geert+renesas@glider.be
| * pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960Geert Uytterhoeven2019-11-015-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_PINCTRL_PFC_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_PINCTRL_PFC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_PINCTRL_PFC_R8A77961. Extend the dependency of CONFIG_PINCTRL_PFC_R8A77960 from CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the SoC configuration symbol. Rename r8a7796_pinmux_info to r8a77960_pinmux_info, as it contains an r8a77960-based name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122955.12420-3-geert+renesas@glider.be
| * pinctrl: sh-pfc: Do not use platform_get_irq() to count interruptsGeert Uytterhoeven2019-11-011-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As platform_get_irq() now prints an error when the interrupt does not exist, counting interrupts by looping until failure causes the printing of scary messages like: sh-pfc e6060000.pin-controller: IRQ index 0 not found Fix this by using the platform_irq_count() helper instead. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191016142601.28255-1-geert+renesas@glider.be
* | Merge tag 'sh-pfc-for-v5.5-tag1' of ↵Linus Walleij2019-10-2511-445/+503
|\| | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.5 - Add support for the new RZ/G2N (r8a774b1) SoC, - Small fixes and cleanups.
| * pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3Keiya Nobuta2019-10-141-1/+1
| | | | | | | | | | | | | | | | SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-4-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3Keiya Nobuta2019-10-141-1/+1
| | | | | | | | | | | | | | | | SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-3-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3Keiya Nobuta2019-10-141-1/+1
| | | | | | | | | | | | | | | | SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-2-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3Keiya Nobuta2019-10-141-1/+1
| | | | | | | | | | | | | | | | SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-1-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSRKeiya Nobuta2019-10-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR. When assigning function to pin, GPSR should be set to peripheral function. For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to peripheral function. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: rzn1: Make array reg_drive static, makes object smallerColin Ian King2019-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate the array reg_drive on the stack but instead make it static. Makes the object code smaller by 32 bytes. Before: text data bss dec hex filename 31991 15696 0 47687 ba47 drivers/pinctrl/pinctrl-rzn1.o After: text data bss dec hex filename 31863 15792 0 47655 ba27 drivers/pinctrl/pinctrl-rzn1.o (gcc version 9.2.1, amd64) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20191007140559.11840-1-colin.king@canonical.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: rza2: Fix gpio name typosChris Brandt2019-10-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix apparent copy/paste errors that were overlooked in the original driver. "P0_4" -> "PF_4" "P0_3" -> "PG_3" Fixes: b59d0e782706 ("pinctrl: Add RZ/A2 pin and gpio controller") Cc: <stable@vger.kernel.org> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Link: https://lore.kernel.org/r/20190930145804.30497-1-chris.brandt@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC supportBiju Das2019-10-015-409/+464
| | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-9-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"Geert Uytterhoeven2019-10-011-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e167d723e1a472d252e5c4baf823b77ce5543b05. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SIMCARD_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-4-geert+renesas@glider.be
| * Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 ↵Geert Uytterhoeven2019-10-011-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and SSI_WS2" This reverts commit e87882eb9be10b2b9e28156922c2a47d877f5db4. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SSI2_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-3-geert+renesas@glider.be
| * pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functionsTakeshi Kihara2019-10-011-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2 register bit[23:20] value H'3 and register bit[27:24] value H'3 from AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp. AVB_AVTP_CAPTURE. Update the R-Car E3 pin control driver to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword, reference errata] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-2-geert+renesas@glider.be
* | pinctrl: mvebu: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-242-8/+3
| | | | | | | | | | | | | | | | | | Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20191016141217.21520-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-241-3/+1
| | | | | | | | | | | | | | | | | | Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20191016141053.23740-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sprd: Add CM4 sleep mode supportBruce Chen2019-10-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | For the new Spreadtrum pin controller, it expands 6bits to describe the pin sleep mode with adding one CM4_SLEEP mode, which means the pin sleep related configuration will be loaded automatically by hardware when the CM4 system goes into deep sleep mode. Signed-off-by: Bruce Chen <bruce.chen@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/8ae52263b0625c416461821c457e6789b67170b6.1571228451.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: Simplify interrupt handlerLinus Walleij2019-10-161-14/+7
| | | | | | | | | | | | | | | | The inner interrupt handler was for the latent IRQ handling, and that will never be used, inline the unnecessary function. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-3-linus.walleij@linaro.org
* | pinctrl: nomadik: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-24/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-2-linus.walleij@linaro.org
* | pinctrl: nomadik: Drop support for latent IRQLinus Walleij2019-10-161-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latent IRQs are IRQs that have occurred when the system was down in deep sleep and the GPIO block was powered off. The PRCMU (power reset and control unit) knows which GPIO line offset fired an IRQ to wake the system up (if so desired) and this second IRQ was used to replay the action when the system came back online after suspend(). This is now known to be the wrong approach to solve this problem: in a patch series Lina Iyer has suggested to instead make it possible to model the IRQs as hierarchical with double parents. Also the current device trees do not contain the right information to make this code work, the latent IRQ is not specified nowadays giving noise like this in the console: [ 0.612168] gpio 8012e000.gpio: IRQ index 1 not found [ 0.622523] gpio 8012e080.gpio: IRQ index 1 not found Let's delete the latent IRQ code and reimplement it properly when we need it. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-1-linus.walleij@linaro.org
* | pinctrl: rockchip: add rk3308 SoC supportJianqun Xu2019-10-161-1/+381
| | | | | | | | | | | | | | | | | | This patch do support pinctrl for RK3308 SoCs. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20191015091708.7934-3-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sprd: Add PIN_CONFIG_BIAS_DISABLE configuration supportBaolin Wang2019-10-161-0/+17
| | | | | | | | | | | | | | | | | | Add PIN_CONFIG_BIAS_DISABLE configuration support for Spreadtrum pin controller. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/66d373ddee61e8be2fcef49aac5e80bd58f14915.1570596606.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stmfx: add irq_request/release_resources callbacksAmelie Delaunay2019-10-161-0/+21
| | | | | | | | | | | | | | | | | | | | | | When an STMFX IO is used as interrupt through the interrupt-controller binding, the STMFX driver should configure this IO as input. Default value of STMFX IO direction is input, but if the IO is used as output before the interrupt use, it will not work without these callbacks. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20191009091606.17283-1-amelie.delaunay@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956AngeloGioacchino Del Regno2019-10-163-0/+1138
| | | | | | | | | | | | | | | | | | | | Add the pinctrl driver to support pin configuration with the pinctrl framework on MSM8976, MSM8956, APQ8056, APQ8076. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191005105936.31216-2-kholk11@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: ingenic: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Zhou Yanjie <zhouyanjie@zoho.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001133209.17164-1-linus.walleij@linaro.org
* | dt-bindings: pinctrl: qcom-pmic-gpio: Add support for pm6150/pm6150lKiran Gunda2019-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add support for the PM6150 and PM6150L GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> Link: https://lore.kernel.org/r/1570188039-22122-1-git-send-email-kgunda@codeaurora.org Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: pistachio: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: James Hartley <james.hartley@sondrel.com> Link: https://lore.kernel.org/r/20191001214536.18477-1-linus.walleij@linaro.org
* | pinctrl: armada-37xx: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Marek Behún <marek.behun@nic.cz> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191002121550.16104-1-linus.walleij@linaro.org
* | pinctrl: ocelot: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20191002114454.9684-1-linus.walleij@linaro.org
* | pinctrl: oxnas: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191002113819.4927-1-linus.walleij@linaro.org
* | pinctrl: st: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-21/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: the ST pin controller errors out of adding a irqchip if the interrupt is invalid or missing or if the irqmux is not present: the irqchip should not be added if either of these errors happen, so rewrite the code to deal with that. Keep the exit path where the gpio_chip is added no matter what the status of the irq is. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001135147.29416-1-linus.walleij@linaro.org
* | pinctrl: at91: Pass irqchip when adding gpiochipLinus Walleij2019-10-161-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: at91 is a little bit special since it registers up to 3 gpio_chips with the same parent handler, but just passing girq->parent_handler and the parent on the first of them should cut it. Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191001130645.8350-1-linus.walleij@linaro.org
* | pinctrl: iproc: use unique name for irq chipChris Packham2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | Use the dev_name(dev) for the irqc->name so that we get unique names when we have multiple instances of this driver. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20191003000310.17099-3-chris.packham@alliedtelesis.co.nz Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: devicetree.c: remove orphan pinctrl_dt_has_hogs()Rasmus Villemoes2019-10-042-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | The helper pinctrl_dt_has_hogs() was introduced in 99e4f67508e1 (pinctrl: core: Use delayed work for hogs), but the sole use then got removed shortly after in 950b0d91dc10 (pinctrl: core: Fix regression caused by delayed work for hogs). Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Link: https://lore.kernel.org/r/20190923142005.5632-1-linux@rasmusvillemoes.dk Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: xusb: Add note about legacy statusThierry Reding2019-10-041-0/+6
| | | | | | | | | | | | | | | | | | | | Add a comment about why the call to of_match_node() cannot be replaced by of_device_get_match_data(). This will hopefully prevent people from attempting to clean this up in the future. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctl: ti: iodelay: fix error checking on pinctrl_count_index_with_args callColin Ian King2019-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to pinctrl_count_index_with_args checks for a -EINVAL return however this function calls pinctrl_get_list_and_count and this can return -ENOENT. Rather than check for a specific error, fix this by checking for any error return to catch the -ENOENT case. Addresses-Coverity: ("Improper use of negative") Fixes: 003910ebc83b ("pinctrl: Introduce TI IOdelay configuration driver") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20190920122030.14340-1-colin.king@canonical.com Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio coreBrian Masney2019-10-032-88/+34
| | | | | | | | | | | | | | | | | | | | Now that the GPIO core has support for hierarchical IRQ chips, convert Qualcomm's ssbi-gpio over to use these new helpers to reduce duplicated code across drivers. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20190914111010.24384-1-masneyb@onstation.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: devicetree: Avoid taking direct reference to device name stringWill Deacon2019-10-031-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When populating the pinctrl mapping table entries for a device, the 'dev_name' field for each entry is initialised to point directly at the string returned by 'dev_name()' for the device and subsequently used by 'create_pinctrl()' when looking up the mappings for the device being probed. This is unreliable in the presence of calls to 'dev_set_name()', which may reallocate the device name string leaving the pinctrl mappings with a dangling reference. This then leads to a use-after-free every time the name is dereferenced by a device probe: | BUG: KASAN: invalid-access in strcmp+0x20/0x64 | Read of size 1 at addr 13ffffc153494b00 by task modprobe/590 | Pointer tag: [13], memory tag: [fe] | | Call trace: | __kasan_report+0x16c/0x1dc | kasan_report+0x10/0x18 | check_memory_region | __hwasan_load1_noabort+0x4c/0x54 | strcmp+0x20/0x64 | create_pinctrl+0x18c/0x7f4 | pinctrl_get+0x90/0x114 | devm_pinctrl_get+0x44/0x98 | pinctrl_bind_pins+0x5c/0x450 | really_probe+0x1c8/0x9a4 | driver_probe_device+0x120/0x1d8 Follow the example of sysfs, and duplicate the device name string before stashing it away in the pinctrl mapping entries. Cc: Linus Walleij <linus.walleij@linaro.org> Reported-by: Elena Petrova <lenaptr@google.com> Tested-by: Elena Petrova <lenaptr@google.com> Signed-off-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20191002124206.22928-1-will@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: at91-pio4: implement .get_multiple and .set_multipleAlexandre Belloni2019-10-031-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement .get_multiple and .set_multiple to allow reading or setting multiple pins simultaneously. Pins in the same bank will all be switched at the same time, improving synchronization and performances. Keep the driver future proof by allowing its use on 64bits platforms if they ever appear with this IP and we end up with a mismatch between ATMEL_PIO_NPINS_PER_BANK and BITS_PER_LONG. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20190918113657.25998-1-alexandre.belloni@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sirf/atlas7: Pass irqchip when adding gpiochipLinus Walleij2019-09-301-20/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Barry Song <baohua@kernel.org> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-6-linus.walleij@linaro.org
* | pinctrl: sirf: Pass irqchip when adding gpiochipLinus Walleij2019-09-301-23/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Barry Song <baohua@kernel.org> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-5-linus.walleij@linaro.org
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 18:11:59 +0100