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* pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flagGeert Uytterhoeven2023-03-3011-63/+63
| | | | | | | | | | | | | | | Commit 537db25ca330dce0 ("pinctrl: renesas: Add I/O voltage level flag") introduced new flags to support pins that can switch their voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. The old SH_PFC_PIN_CFG_IO_VOLTAGE flag was retained to avoid having to change existing drivers. Replace SH_PFC_PIN_CFG_IO_VOLTAGE by SH_PFC_PIN_CFG_IO_VOLTAGE_18_33, to make the voltage configuration explicit, and to prepare for the advent of support for more voltage levels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ae5f879c093f3e3cd50ba1495975bccfad81237b.1678271030.git.geert+renesas@glider.be
* pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resumeGeert Uytterhoeven2023-03-301-10/+13
| | | | | | | | | | | | | | | | The POC Control Register 0 (POCCTRL0) on R-Car D3 is not registered in the pinmux_ioctrl_regs[] array. Hence it is not saved/restored during suspend/resume, and its contents may be lost after s2ram. This went unnoticed when improving suspend/resume support in commit d92ee9cf8ec8d7fe ("pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume"). Fix this by moving the pinmux_ioctrl_regs[] array up, and adding the POCCTRL0 register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d17402b83b1f3fa0f572527c0382027bccb86205.1678271030.git.geert+renesas@glider.be
* pinctrl: renesas: Drop support for Renesas-specific propertiesGeert Uytterhoeven2023-03-161-26/+5
| | | | | | | | | | The last user of the Renesas-specific properties was converted to the standard properties in commit af897250ea54c6f2 ("ARM: dts: gose: use generic pinctrl properties in SDHI nodes") in v4.10. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/ff9c14781110bbf19b56b45dd1f01e6da90319ad.1678704441.git.geert+renesas@glider.be
* pinctrl: renesas: Remove R-Car H3 ES1.* handlingWolfram Sang2023-03-105-5992/+3
| | | | | | | | | | | | | R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230307105645.5285-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: renesas: r8a779g0: Fix ERROROUTC function namesGeert Uytterhoeven2023-03-101-251/+251
| | | | | | | | | | | | | | According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, the ERROROUTC signal is active-low. Hence add the missing "_N" suffix to the pin function's names. Resize column 2 of all IPxSR* definitions to accomodate the longer names. Fixes: b811062e5fd0343c ("pinctrl: renesas: r8a779g0: Add missing ERROROUTC_A") Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1774303989e7d61f08fa81f1c2fa1b394505645f.1669036423.git.geert+renesas@glider.be
* pinctrl: renesas: r8a779g0: Fix Group 6/7 pin functionsGeert Uytterhoeven2023-03-101-122/+49
| | | | | | | | | | | | | | | According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, pin groups 6 and 7 do not use Module Select Registers to configure pin functions. Hence: - Remove the non-existent Module Select Registers (MODSEL[67]), - Correct the affected PINMUX definitions. Fixes: 36611d28f5130d8b ("pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx") Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/06972cafd0efa4cfb395cfa76000a1bdae5e9e73.1669036423.git.geert+renesas@glider.be
* pinctrl: renesas: r8a779g0: Fix Group 4/5 pin functionsGeert Uytterhoeven2023-03-101-188/+279
| | | | | | | | | | | | | | | | | | | According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, pin groups 4 and 5 do not use Module Select Registers to configure pin functions, but use Peripheral Function Select Registers instead. Hence: - Remove the non-existent Module Select Registers (MODSEL[45]), - Add the missing Peripheral Function Select Registers (IPxSR[45]), - Correct the GPIO / Peripheral Function Select Register definitions (GPSR]45_*), - Correct the affected PINMUX definitions. Fixes: 36611d28f5130d8b ("pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx") Fixes: 36fb7b8af55b83e0 ("pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0") Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3d3833d1738f5e8fcc4c1002aa93832464d129a0.1669036423.git.geert+renesas@glider.be
* pinctrl: renesas: r8a779g0: Add Audio SSI pins, groups, and functionsLinh Phung2023-03-061-0/+26
| | | | | | | | | | | Add pins, groups, and functions for the Serial Sound Interface (SSI) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87bkmcang2.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: renesas: r8a779g0: Add Audio Clock pins, groups, and functionsLinh Phung2023-03-061-0/+26
| | | | | | | | | | | Add pins, groups, and functions for the Audio Clock on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87cz6sanga.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: renesas: r8a779f0: Fix tsn1_avtp_pps pin groupPhong Hoang2023-03-061-1/+1
| | | | | | | | | | Correct a typo mistake in the definition of the tsn1_avtp_pps pin group mux. Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Fixes: babe298e9caaa3d7 ("pinctrl: renesas: r8a779f0: Add Ethernet pins, groups, and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/45ea6e87b91c36fd0b9706cf58ff50a4d1a99c44.1674825039.git.geert+renesas@glider.be
* pinctrl: renesas: r8a779a0: Remove incorrect AVB[01] pinmux configurationHai Pham2023-03-061-8/+0
| | | | | | | | | | | | | | AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array. The latter are correct, hence remove the former. Without this fix, the Ethernet PHY is not operational on the MDIO bus. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be
* Merge tag 'soc-drivers-6.3' of ↵Linus Torvalds2023-02-271-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "As usual, there are lots of minor driver changes across SoC platforms from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung. These usually add support for additional chip variations in existing drivers, but also add features or bugfixes. The SCMI firmware subsystem gains a unified raw userspace interface through debugfs, which can be used for validation purposes. Newly added drivers include: - New power management drivers for StarFive JH7110, Allwinner D1 and Renesas RZ/V2M - A driver for Qualcomm battery and power supply status - A SoC device driver for identifying Nuvoton WPCM450 chips - A regulator coupler driver for Mediatek MT81xxv" * tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) power: supply: Introduce Qualcomm PMIC GLINK power supply soc: apple: rtkit: Do not copy the reg state structure to the stack soc: sunxi: SUN20I_PPU should depend on PM memory: renesas-rpc-if: Remove redundant division of dummy soc: qcom: socinfo: Add IDs for IPQ5332 and its variant dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its variant dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/ MAINTAINERS: Update qcom CPR maintainer entry dt-bindings: firmware: document Qualcomm SM8550 SCM dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants dt-bindings: arm: qcom,ids: Add Soc IDs for IPQ8064 and variants soc: qcom: socinfo: Add support for new field in revision 17 soc: qcom: smd-rpm: Add IPQ9574 compatible soc: qcom: pmic_glink: remove redundant calculation of svid soc: qcom: stats: Populate all subsystem debugfs files dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies soc: qcom: pmic_glink: Introduce altmode support ...
| * firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/Elliot Berman2023-02-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Move include/linux/qcom_scm.h to include/linux/firmware/qcom/qcom_scm.h. This removes 1 of a few remaining Qualcomm-specific headers into a more approciate subdirectory under include/. Suggested-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com> Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Acked-by: Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230203210956.3580811-1-quic_eberman@quicinc.com
* | Merge tag 'pinctrl-v6.3-1' of ↵Linus Torvalds2023-02-2277-651/+9290
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Nothing special, notably a lot of new Qualcomm hardware is supported, a RISC-V reference SoC and then some cleanups both in code and device tree bindings. Core changes: - Add PINCTRL_PINFUNCTION() macro and use it in several drivers New drivers: - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on) pin controllers. (RISC-V.) - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin controllers - New subdriver for the Qualcomm SA8775P SoC pin controller - New subdriver for the Qualcomm IPQ5332 SoC pin controller - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin control - New subdriver for the Mediatek MT7981 SoC pin controller Improvements: - Several cleanups and refactorings to the Intel drivers - Add 4KOhm bias support to the Intel driver - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver - Support general purpose clocks in the Qualcomm MSM8226 SoC - Several conversions to use the new I2C .probe_new() call - Massive clean-up of the Qualcomm Device Tree YAML schemas - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC driver" * tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits) pinctrl: qcom: Add support for i2c specific pull feature pinctrl: starfive: Add StarFive JH7110 aon controller driver pinctrl: starfive: Add StarFive JH7110 sys controller driver dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl pinctrl: add mt7981 pinctrl driver dt-bindings: pinctrl: add bindings for MT7981 SoC dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated pinctrl: qcom: Introduce IPQ5332 TLMM driver dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS pinctrl: at91: use devm_kasprintf() to avoid potential leaks dt-bindings: pinctrl: qcom: correct gpio-ranges in examples dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example ...
| * | pinctrl: qcom: Add support for i2c specific pull featureAbel Vesa2023-02-103-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new i2c_pull property introduced for SM8550 setting a I2C specific pull mode on I2C able pins. Add the bit to the SM8550 specific driver while at it. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209074510.4153294-1-abel.vesa@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: starfive: Add StarFive JH7110 aon controller driverJianlong Huang2023-02-103-0/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver for StarFive JH7110 SoC aon pinctrl controller. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230209143702.44408-5-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: starfive: Add StarFive JH7110 sys controller driverJianlong Huang2023-02-105-0/+1525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230209143702.44408-4-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: add mt7981 pinctrl driverDaniel Golle2023-02-073-0/+1054
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver which can also be found the SDK. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: Introduce IPQ5332 TLMM driverKathiravan T2023-02-073-0/+872
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230206071217.29313-3-quic_kathirav@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASSKrzysztof Kozlowski2023-02-063-0/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add druver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8450 LPASS pin controller, with differences in few pin groups (qua_mi2s -> i2s0). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230203174645.597053-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: at91: use devm_kasprintf() to avoid potential leaksClaudiu Beznea2023-02-062-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_kasprintf() instead of kasprintf() to avoid any potential leaks. At the moment drivers have no remove functionality thus there is no need for fixes tag. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230203132714.1931596-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: add the tlmm driver sa8775p platformsYadu MG2023-02-013-0/+1547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Lemans TLMM configuration and control via the pinctrl framework. Signed-off-by: Yadu MG <quic_ymg@quicinc.com> Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com> [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230201150011.200613-3-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'intel-pinctrl-v6.3-1' of ↵Linus Walleij2023-01-3022-315/+177
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.3-1 * Add ~4kOhm bias support to Intel pin control drivers * Convert Intel pin control drivers to use INTEL_COMMUNITY_*() * Add struct pinfunction and use it in Intel pin control drivers * Make pin control documentation up to date * Miscellaneous cleanups The following is an automated git shortlog grouped by driver: pinctrl: - Proofreading and updating the documentation accordingly - Proofreading and updating the documentation (part 2) alderlake: - Replace ADL_COMMUNITY() by INTEL_COMMUNITY_GPPS() baytrail: - Convert to use new memeber in struct intel_function broxton: - Replace BXT_COMMUNITY() by INTEL_COMMUNITY_SIZE() cannonlake: - Replace CNL_COMMUNITY() by INTEL_COMMUNITY_GPPS() cedarfork: - Replace CDF_COMMUNITY() by INTEL_COMMUNITY_GPPS() cherryview: - Convert to use new memeber in struct intel_function denverton: - Replace DNV_COMMUNITY() by INTEL_COMMUNITY_GPPS() elkhartlake: - Replace EHL_COMMUNITY() by INTEL_COMMUNITY_GPPS() emmitsburg: - Replace EBG_COMMUNITY() by INTEL_COMMUNITY_GPPS() geminilake: - Replace GLK_COMMUNITY() by INTEL_COMMUNITY_SIZE() icelake: - Replace ICL_COMMUNITY() by INTEL_COMMUNITY_GPPS() intel: - Get rid of unused members in struct intel_function - Make use of struct pinfunction and PINCTRL_PINFUNCTION() - Define maximum pad number in the group - Use same order of bit fields for PADCFG2 - Add ~4k bias support - Add definitions to all possible biases - Deduplicate some code in intel_config_set_pull() - Add default case to intel_config_set_pull() - Convert to generic_handle_domain_irq() - Always use gpp_num_padown_regs in the main driver - Introduce INTEL_COMMUNITY_*() to unify community macros Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro: - Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro jasperlake: - Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS() lakefield: - Replace LKF_COMMUNITY() by INTEL_COMMUNITY_GPPS() lewisburg: - Replace LBG_COMMUNITY() by INTEL_COMMUNITY_SIZE() lynxpoint: - Convert to use new memeber in struct intel_function merrifield: - Convert to use new memeber in struct intel_function meteorlake: - Replace MTL_COMMUNITY() by INTEL_COMMUNITY_GPPS() moorefield: - Convert to use new memeber in struct intel_function sunrisepoint: - Replace SPT_COMMUNITY() by INTEL_COMMUNITY_*() tigerlake: - Replace TGL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
| | * | pinctrl: intel: Get rid of unused members in struct intel_functionAndy Shevchenko2022-12-301-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver has been converted to a generic data type and macro for the pin function definition, hence get rid of not used members in the struct intel_function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: moorefield: Convert to use new memeber in struct intel_functionAndy Shevchenko2022-12-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: merrifield: Convert to use new memeber in struct intel_functionAndy Shevchenko2022-12-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: lynxpoint: Convert to use new memeber in struct intel_functionAndy Shevchenko2022-12-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: cherryview: Convert to use new memeber in struct intel_functionAndy Shevchenko2022-12-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: baytrail: Convert to use new memeber in struct intel_functionAndy Shevchenko2022-12-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Make use of struct pinfunction and PINCTRL_PINFUNCTION()Andy Shevchenko2022-12-302-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pin control provides a generic data type and a macro for the pin function definition, use them in the Intel driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Define maximum pad number in the groupAndy Shevchenko2022-12-282-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using hard coded magic number here and there, define maximum pad number in the group in newly added INTEL_PINCTRL_MAX_GPP_SIZE. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Use same order of bit fields for PADCFG2Andy Shevchenko2022-12-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Add ~4k bias supportAndy Shevchenko2022-12-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All versions that have 20k and 5k resistance, i.e. all that the driver supports, may support ~4k when the above mentioned are connected in parallel. Add such a support. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Add definitions to all possible biasesAndy Shevchenko2022-12-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add definitions to all possible biases, i.e. add ~800 Ohms, ~952 Ohms, ~4 kOhms. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Deduplicate some code in intel_config_set_pull()Andy Shevchenko2022-12-281-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First part is to assign default argument for all cases, since bias disablement doesn't use it anyway. Second part is to clear all bits in the bias setting and depending on the argument and parameter set them as asked. While at it, add break statement to the default cases. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Add default case to intel_config_set_pull()Andy Shevchenko2022-12-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the sake of symmetry with intel_config_get_pull(), add a default case to the outer switch. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Convert to generic_handle_domain_irq()Andy Shevchenko2022-12-271-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace construct that matches generic_handle_irq(irq_find_mapping()) to a single call to generic_handle_domain_irq(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Always use gpp_num_padown_regs in the main driverAndy Shevchenko2022-12-272-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the size-based communities, always use gpp_num_padown_regs, which is now provided explicitly via INTEL_COMMUNITY_SIZE() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: sunrisepoint: Replace SPT_COMMUNITY() by INTEL_COMMUNITY_*()Andy Shevchenko2022-12-271-24/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_*() common macro instead custom SPT_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: tigerlake: Replace TGL_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom TGL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: meteorlake: Replace MTL_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom MTL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: lewisburg: Replace LBG_COMMUNITY() by INTEL_COMMUNITY_SIZE()Andy Shevchenko2022-12-271-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_SIZE() common macro instead custom LBG_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: lakefield: Replace LKF_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom LKF_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: jasperlake: Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom JSL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: icelake: Replace ICL_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-22/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom ICL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: geminilake: Replace GLK_COMMUNITY() by INTEL_COMMUNITY_SIZE()Andy Shevchenko2022-12-271-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_SIZE() common macro instead custom GLK_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: emmitsburg: Replace EBG_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom EBG_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: elkhartlake: Replace EHL_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-17/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom EHL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: denverton: Replace DNV_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom DNV_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: cedarfork: Replace CDF_COMMUNITY() by INTEL_COMMUNITY_GPPS()Andy Shevchenko2022-12-271-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use INTEL_COMMUNITY_GPPS() common macro instead custom CDF_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-26 18:30:00 +0100