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* Merge tag 'pinctrl-v5.8-1' of ↵Linus Torvalds2020-06-0861-1288/+3343
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.8 kernel cycle. It's just really boring this time. Zero core changes. Just linear development, cleanups and misc noncritical fixes. Some new drivers for very new Qualcomm and Intel chips. New drivers: - Intel Jasper Lake support. - NXP Freescale i.MX8DXL support. - Qualcomm SM8250 support. - Renesas R8A7742 SH-PFC support. Driver improvements: - Severe cleanup and modernization of the MCP23s08 driver. - Mediatek driver modularized. - Setting config supported in the Meson driver. - Wakeup support for the Broadcom BCM7211" * tag 'pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sprd: Fix the incorrect pull-up definition pinctrl: pxa: pxa2xx: Remove 'pxa2xx_pinctrl_exit()' which is unused and broken pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in case of error in 'imx_pinctrl_probe()' pinctrl: freescale: imx: Fix an error handling path in 'imx_pinctrl_probe()' pinctrl: sirf: add missing put_device() call in sirfsoc_gpio_probe() pinctrl: imxl: Fix an error handling path in 'imx1_pinctrl_core_probe()' pinctrl: bcm2835: Add support for wake-up interrupts pinctrl: bcm2835: Match BCM7211 compatible string dt-bindings: pinctrl: Document optional BCM7211 wake-up interrupts dt-bindings: pinctrl: Document 7211 compatible for brcm, bcm2835-gpio.txt dt-bindings: pinctrl: stm32: Add missing interrupts property pinctrl: at91-pio4: Add COMPILE_TEST support pinctrl: Fix return value about devm_platform_ioremap_resource() MAINTAINERS: Renesas Pin Controllers are supported dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 pinctrl: ocelot: Remove instance number from pin functions pinctrl: ocelot: Always register GPIO driver dt-bindings: pinctrl: rockchip: update example pinctrl: amd: Add ACPI dependency ...
| * pinctrl: sprd: Fix the incorrect pull-up definitionBaolin Wang2020-06-041-2/+2
| | | | | | | | | | | | | | | | | | | | The bits of pull up resistor selection were defined mistakenly, thus fix them. Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/e973f8f194ce4cb2639121572e8621b5efa5bfbe.1588823152.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pxa: pxa2xx: Remove 'pxa2xx_pinctrl_exit()' which is unused and brokenChristophe JAILLET2020-06-041-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6d33ee7a0534 ("pinctrl: pxa: Use devm_pinctrl_register() for pinctrl registration") has turned a 'pinctrl_register()' into 'devm_pinctrl_register()' in 'pxa2xx_pinctrl_init()'. However, the corresponding 'pinctrl_unregister()' call in 'pxa2xx_pinctrl_exit()' has not been removed. This is not an issue, because 'pxa2xx_pinctrl_exit()' is unused. Remove it now to avoid some wondering in the future and save a few LoC. Fixes: 6d33ee7a0534 ("pinctrl: pxa: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Link: https://lore.kernel.org/r/20200531073716.593343-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in ↵Christophe JAILLET2020-06-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | case of error in 'imx_pinctrl_probe()' Use 'devm_of_iomap()' instead 'of_iomap()' to avoid a resource leak in case of error. Update the error handling code accordingly. Fixes: 26d8cde5260b ("pinctrl: freescale: imx: add shared input select reg support") Suggested-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20200602200626.677981-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: freescale: imx: Fix an error handling path in 'imx_pinctrl_probe()'Christophe JAILLET2020-06-031-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pinctrl_unregister()' should not be called to undo 'devm_pinctrl_register_and_init()', it is already handled by the framework. This simplifies the error handling paths of the probe function. The 'imx_free_resources()' can be removed as well. Fixes: a51c158bf0f7 ("pinctrl: imx: use radix trees for groups and functions") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20200530204955.588962-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sirf: add missing put_device() call in sirfsoc_gpio_probe()yu kuai2020-06-031-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A coccicheck run provided information like the following: drivers/pinctrl/sirf/pinctrl-sirf.c:798:2-8: ERROR: missing put_device; call of_find_device_by_node on line 792, but without a corresponding object release within this function. Generated by: scripts/coccinelle/free/put_device.cocci Thus add a jump target to fix the exception handling for this function implementation. Fixes: 5130216265f6 ("PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII") Signed-off-by: yu kuai <yukuai3@huawei.com> Link: https://lore.kernel.org/r/20200603013532.755220-1-yukuai3@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imxl: Fix an error handling path in 'imx1_pinctrl_core_probe()'Christophe JAILLET2020-06-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | When 'pinctrl_register()' has been turned into 'devm_pinctrl_register()', an error handling path has not been updated. Axe a now unneeded 'pinctrl_unregister()'. Fixes: e55e025d1687 ("pinctrl: imxl: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200530201952.585798-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm2835: Add support for wake-up interruptsFlorian Fainelli2020-06-031-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leverage the IRQCHIP_MASK_ON_SUSPEND flag in order to avoid having to specifically treat the GPIO interrupts during suspend and resume, and simply implement an irq_set_wake() callback that is responsible for enabling the parent wake-up interrupt as a wake-up interrupt. To avoid allocating unnecessary resources for other chips, the wake-up interrupts are only initialized if we have a brcm,bcm7211-gpio compatibility string. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20200531001101.24945-5-f.fainelli@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm2835: Match BCM7211 compatible stringFlorian Fainelli2020-06-031-0/+4
| | | | | | | | | | | | | | | | | | | | The BCM7211 SoC uses the same pinconf_ops as the ones defined for the BCM2711 SoC, match the compatible string and use the correct set of options. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20200531001101.24945-4-f.fainelli@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91-pio4: Add COMPILE_TEST supportTiezhu Yang2020-05-251-1/+1
| | | | | | | | | | | | | | | | | | Add COMPILE_TEST support to the AT91 PIO4 pinctrl driver for better compile testing coverage. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1590234326-2194-2-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Fix return value about devm_platform_ioremap_resource()Tiezhu Yang2020-05-252-2/+2
| | | | | | | | | | | | | | | | | | | | When call function devm_platform_ioremap_resource(), we should use IS_ERR() to check the return value and return PTR_ERR() if failed. Fixes: 4b024225c4a8 ("pinctrl: use devm_platform_ioremap_resource() to simplify code") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1590234326-2194-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v5.8-tag2' of ↵Linus Walleij2020-05-256-353/+405
| |\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.8 (take two) - Add support for the new RZ/G1H (r8a7742) SoC, - Minor fixes and improvements.
| | * pinctrl: rza1: Fix flag name in commentGeert Uytterhoeven2020-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | rza1_swio_pin relates to the swio flag instead of the bidir flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20200507074516.29903-1-geert+renesas@glider.be
| | * pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC supportLad Prabhakar2020-05-155-352/+404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | Merge tag 'samsung-pinctrl-5.8' of ↵Linus Walleij2020-05-191-24/+58
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.8 Two fixes for S5Pv210 pinctrl driver: setting proper external interrupt wakeup mask and restoring external interrupt mask value after system suspend.
| | * | pinctrl: samsung: Save/restore eint_mask over suspend for EINT_TYPE GPIOsJonathan Bakker2020-04-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers are saved and restored over a suspend/resume cycle. However, the EINT_MASK registers are not. On S5PV210 at the very least, these registers are not retained over suspend, leading to the interrupts remaining masked upon resume and therefore no interrupts being triggered for the device. There should be no effect on any SoCs that do retain these registers as theoretically we would just be re-writing what was already there. Fixes: 7ccbc60cd9c2 ("pinctrl: exynos: Handle suspend/resume of GPIO EINT registers") Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | pinctrl: samsung: Correct setting of eint wakeup mask on s5pv210Jonathan Bakker2020-04-131-24/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a8be2af0218c ("pinctrl: samsung: Write external wakeup interrupt mask") started writing the eint wakeup mask from the pinctrl driver. Unfortunately, it made the assumption that the private retention data was always a regmap while in the case of s5pv210 it is a raw pointer to the clock base (as the eint wakeup mask not in the PMU as with newer Exynos platforms). Fixes: a8be2af0218c ("pinctrl: samsung: Write external wakeup interrupt mask") Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2Lars Povlsen2020-05-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem with using the GPIO as an interrupt on Jaguar2 (and similar), as the register layout of the platforms with 64 GPIO's are pairwise, such that the original offset must be multiplied with the platform stride. Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200513125532.24585-4-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ocelot: Remove instance number from pin functionsLars Povlsen2020-05-181-64/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the instance number from the "miim", "reco_clk" and "sfp" pin function. The change needed is to prepare the driver for adding new platforms with more of these instances. The instance number is also redundant, as this is implicit for each pin. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200513125532.24585-3-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ocelot: Always register GPIO driverLars Povlsen2020-05-181-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the situation where the GPIO controller is not used as an interrupt controller as well. Previously, the driver would silently fail to register even the GPIO's. With this change, the driver will only register as an interrupt controller if a parent interrupt is provided. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200513125532.24585-2-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: amd: Add ACPI dependencyGeert Uytterhoeven2020-05-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the AMD pin controller driver supports ACPI platform only. Make the PINCTRL_AMD config symbol depend on ACPI, to avoid asking the user about it when configuring a kernel without ACPI support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113751.24213-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: equilibrium: Add architecture dependencyGeert Uytterhoeven2020-05-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Equilibrium pin controller is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PINCTRL_EQUILIBRIUM config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113626.24026-2-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'intel-pinctrl-v5.8-1' of ↵Linus Walleij2020-05-1512-266/+573
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.8-1 * Introduce GPIO driver for Jasper Lake * Fix long standing bug in Sunrisepoint-H PAD locking code * Enable pin configuration setting for GPIO chip for Baytrail * Work around race condition in Cherriview hardware when handle IRQ * Clean up Cherryview code to be closer to other drivers The following is an automated git shortlog grouped by driver: baytrail: - Use platform_get_irq_optional() explicitly - Enable pin configuration setting for GPIO chip cannonlake: - Use generic flag for special GPIO base treatment cherryview: - Add missing spinlock usage in chv_gpio_irq_handler - Use GENMASK() consistently - Re-use data structures from pinctrl-intel.h (part 2) icelake: - Use generic flag for special GPIO base treatment intel: - Move npins closer to pin_base in struct intel_community - Update description in struct intel_community - Add Intel Jasper Lake pin controller support - Introduce new flag to force GPIO base to be 0 - Introduce common flags for GPIO mapping scheme lynxpoint: - Use platform_get_irq_optional() explicitly sunrisepoint: - Fix PAD lock register offset for SPT-H tigerlake: - Use generic flag for special GPIO base treatment
| | * | | pinctrl: intel: Move npins closer to pin_base in struct intel_communityAndy Shevchenko2020-04-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's common across the drivers to use the (pin_base, npins) pair to describe community characteristics. Thus, move them in the struct intel_community to be closer to each other. While at it, add a blank line to cut driver usable fields from what core reserves for itself. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: intel: Update description in struct intel_communityAndy Shevchenko2020-04-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that most of the drivers, that are using struct intel_community, utilize gpps rather than gpp_size. Update comment accordingly. While here, correct the description of gpp_size, i.e. remove double space and drop redundant 'etc.' part. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handlerGrace Kao2020-04-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e. cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler") Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers") Signed-off-by: Grace Kao <grace.kao@intel.com> Reported-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | | pinctrl: lynxpoint: Use platform_get_irq_optional() explicitlyAndy Shevchenko2020-04-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to repeat functionality of platform_get_irq_optional() in the driver. Replace it with explicit call to the helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | pinctrl: baytrail: Use platform_get_irq_optional() explicitlyAndy Shevchenko2020-04-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to repeat functionality of platform_get_irq_optional() in the driver. Replace it with explicit call to the helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: intel: Add Intel Jasper Lake pin controller supportAndy Shevchenko2020-04-143-0/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: intel: Introduce new flag to force GPIO base to be 0Andy Shevchenko2020-04-142-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases not the first group would like to have GPIO base to be 0. It's not possible right now due to 0 has special meaning already. Thus, introduce a new flag to allow drivers to force GPIO base to be 0 on a certain group. It's assumed that it can be only one group per device with such flag enabled. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: tigerlake: Use generic flag for special GPIO base treatmentAndy Shevchenko2020-04-141-17/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: icelake: Use generic flag for special GPIO base treatmentAndy Shevchenko2020-04-141-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: cannonlake: Use generic flag for special GPIO base treatmentAndy Shevchenko2020-04-141-30/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: intel: Introduce common flags for GPIO mapping schemeAndy Shevchenko2020-04-142-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few drivers are using the same flag to tell Intel pin control core how to interpret GPIO base. Provide a generic flags so all drivers can use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: cherryview: Use GENMASK() consistentlyAndy Shevchenko2020-04-131-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use GENMASK() macro for all definitions where it's appropriate. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | | pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 2)Andy Shevchenko2020-04-131-165/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have some data structures duplicated across the drivers. Let's deduplicate them by using ones that being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * | | | pinctrl: rockchip: fix memleak in rockchip_dt_node_to_mapDafna Hirschfeld2020-05-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function rockchip_dt_node_to_map, a new_map variable is allocated by: new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL); This uses devres and attaches new_map to the pinctrl driver. This cause a leak since new_map is not released when the probed driver is removed. Fix it by using kcalloc to allocate new_map and free it in `rockchip_dt_free_map` Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20200506100903.15420-1-dafna.hirschfeld@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: rockchip: return ENOMEM instead of EINVAL if allocation failsDafna Hirschfeld2020-05-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function rockchip_pinctrl_parse_dt returns -EINVAL if allocation fails. Change the return error to -ENOMEM Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20200506101424.15691-1-dafna.hirschfeld@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: mediatek: add pinctrl-mtk-common-v2 module licenseArnd Bergmann2020-05-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kbuild warns when this file is built as a loadable module: WARNING: modpost: missing MODULE_LICENSE() in drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o see include/linux/module.h for more information Add the missing license/author/description tags. Fixes: 8174a8512e3e ("pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200505140848.554957-1-arnd@arndb.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: ingenic: Add irq_{request,release}_resources callbacksPaul Cercueil2020-05-121-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are called when a GPIO is to be used as IRQ. Without these custom callbacks, when an interrupt is requested directly and not through gpiod_to_irq(), the request fails because the GPIO is not necesarily in input mode. These callbacks simply enforce that the requested GPIO is in input mode. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: rk805: Constify rk805_gpio_cfgsRikard Falkeborn2020-05-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark pin_cfg as const, allowing the compiler to put the struct in .rodata instead of .data. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200425203813.6442-1-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | Merge tag 'sh-pfc-for-v5.8-tag1' of ↵Linus Walleij2020-05-091-1/+1
| |\ \ \ \ | | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.8 - Fix SWIO pins on RZ/A1L, - Add missing bindings to MAINTAINERS.
| | * | | pinctrl: rza1: Fix wrong array assignment of rza1l_swio_entriesJason Yan2020-04-201-1/+1
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rza1l_swio_entries referred to the wrong array rza1h_swio_pins, which was intended to be rza1l_swio_pins. So let's fix it. This is detected by the following gcc warning: drivers/pinctrl/pinctrl-rza1.c:401:35: warning: ‘rza1l_swio_pins’ defined but not used [-Wunused-const-variable=] static const struct rza1_swio_pin rza1l_swio_pins[] = { ^~~~~~~~~~~~~~~ Fixes: 039bc58e73b77723 ("pinctrl: rza1: Add support for RZ/A1L") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200417111604.19143-1-yanaijie@huawei.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | pinctrl: db8500: Fix some old bugsLinus Walleij2020-04-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hulk robot reports these build warnings: drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:899:20: warning: ‘sbag_groups’ defined but not used [-Wunused-const-variable=] DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1"); ^ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:570:23: warning: ‘ipgpio6_c_2_pins’ defined but not used [-Wunused-const-variable=] static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; ^~~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:472:23: warning: ‘mc1dir_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, ^~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:453:23: warning: ‘modem_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, ^~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:430:23: warning: ‘kpskaskb_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; ^~~~~~~~~~~~~~~~~ They are just very old bugs in seldomly used pin groups. Fix the problem by using the pins and referencing the function. Reported-by: Hulk Robot <hulkci@huawei.com> Reported-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ab8505: Define group for GPIO pin 50Linus Walleij2020-04-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hulk robot reports an usused varible: drivers/pinctrl/nomadik/pinctrl-ab8505.c:137:23: warning: ‘gpio50_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; ^~~~~~~~~~~~~~~ This variable actually should be used. Probably an oversight by the driver author. Cc: Patrice Chotard <patrice.chotard@st.com> Reported-by: Hulk Robot <hulkci@huawei.com> Reported-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: bm1880: add pwm37 to bm1880_pctrl_groupsJason Yan2020-04-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'pwm37' is not added to bm1880_pctrl_groups, which triggers a gcc build warning: drivers/pinctrl/pinctrl-bm1880.c:263:27: warning: ‘pwm37_pins’ defined but not used [-Wunused-const-variable=] static const unsigned int pwm37_pins[] = { 110 }; Signed-off-by: Jason Yan <yanaijie@huawei.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200428115543.33379-1-yanaijie@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: stmfx: stmfx_pinconf_set doesn't require to get direction anymoreAmelie Delaunay2020-04-281-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin direction is not used to set pin configuration. Fixes: a502b343ebd0 ("pinctrl: stmfx: update pinconf settings") Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20200422072513.8352-1-amelie.delaunay@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: fix several typosDejin Zheng2020-04-286-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use codespell to fix lots of typos over frontends. Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> CC: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200421142402.9524-1-zhengdejin5@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: wire up the gpio_chip's set_config callbackMartin Blumenstingl2020-04-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use gpiochip_generic_config for the gpio_chip's set_config callback so GPIO flags like GPIO_PULL_UP or GPIO_PULL_DOWN can be used in the board .dts descriptions. This is required for some Meson8m2 boards where GPIO_BSD_EN provides the "MUTE" signal and requires enabling the internal pull-up resistor. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200417183349.1283092-3-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: implement the gpio_chip get_direction callbackMartin Blumenstingl2020-04-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the get_direction callback so we read the direction from the actual GPIO controller register. This is recommended by the gpio_chip kernel doc. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200417183349.1283092-2-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 03:53:02 +0100