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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"For this kernel cycle I managed an immutable branch for the PEF2256
WAN framer that has some pin control portions. It already landed in
your tree through the net pull request but here it is mentioned again.
The most interesting is perhaps the Samsung Exynos subdrivers for the
Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for
automotive. Along with the earlier merged Tesla FSD subdriver it shows
some of the versatile uses of the Samsung Exynos silicon. It is also
used in the latest version of Axis Communications ARTPEC chips so it
is a very widely deployed SoC family.
We also have the Intel Meteor Lake SoC which I think is for laptops.
It's a pretty interesting chip with Xe graphics and integrated PCH.
Core changes:
- A new PINCTRL_GROUP_DESC() infrastructure macro is added and used
in different drivers, generic group description struct group_desc
is now used all over the place.
New drivers:
- New driver for the Texas Instruments TPS6494 Power Management IC.
- New driver for the Lantic PEF2256 framer pin multiplexer. This IC
has some pins that can be reconfigured in different ways. The
actual driver comes on an immutable branch with the net WAN parts,
the IC is some latest-and-greatest serial line funnel for e.g.
wireless access points.
- New subdriver for the Samsung Exynos Auto V920 pin controller, used
for automotive applications.
- New subdriver for the Samsung "GS101" SoC pin controller, this is
the Google "Tensor" SoC used in the Google Pixel 6.
- New subdriver for the Intel Meteor Point SoC pin controller.
- New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS
pin controllers.
- New subdriver for the Qualcomm X1E80100 top level (TLMM) pin
controller.
- New subdriver for the Qualcomm SM4450 top level (TLMM) pin
controller.
- The "single" pin controller now supports the Texas Instruments
J7200 SoC.
Improvements:
- Intel has created a new (Intel-)generic pin controller driver that
is now used by all contemporary Intel platforms.
- Intel is now also making use of some cleanup helpers.
- Enble 910 Ohm bias in the Intel Tangier driver.
- The Samsung driver now suppors irq_set_affinity() in it's IRQ chip
giving support for non wake up external gpio interrupts"
* tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: samsung: constify iomem pointers
pinctrl: cy8c95x0: Cache muxed registers
dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp
pinctrl: qcom: lpass-lpi: remove duplicated include
dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent
dt-bindings: pinctrl: qcom: drop common properties
dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings
dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom: create common LPASS LPI schema
pinctrl: qcom: sm4450: dd SM4450 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
dt-bindings: pinctrl: qcom,pmic-mpp: clean up example
pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support
pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins
pinctrl: renesas: rzg2l: Add output enable support
...
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Constify few pointers to iomem, where the destination memory is not
modified, for code safety and readability.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20231223191902.22857-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Currently the port specific registers behind the PORTSEL mux aren't
cached in the regmap and thus the typical setup time for a single pin
on cy8c9560 is about 200msec on our system. The hotspot is the IRQ
(un)masking, which causes lots of R/W operations.
Introduce a separate regmap for muxed registers and helper functions
to use the newly introduced regmap for muxed register access under
the i2c lock.
With the new cache in place the typical pin setup time is reduced to
20msec, making it about 10 times faster. As a side effect the system
boot time is also reduced by 50%.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20231219125350.4031370-1-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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remove the second #include <linux/seq_file.h>
Signed-off-by: Wang Jinchao <wangjinchao@xfusion.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/202312151810+0800-wangjinchao@xfusion.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pinctrl driver for TLMM block found in SM4450 SoC.
Can Guo helped out in reviewing the driver.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.8-1
* New agnostic driver to support Lunar Lake and newer platforms
* New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
* Update drivers to use new PM helpers
* Use RAII for locking in a few drivers (Raag, Andy)
* Reduce locking scope in some functions (Raag)
* Miscellaneous cleanups (Raag)
The following is an automated git shortlog grouped by driver:
alderlake:
- Switch to use Intel pin control PM ops
baytrail:
- Simplify code with cleanup helpers
- Move default strength assignment to a switch-case
- Factor out byt_gpio_force_input_mode()
- Fix types of config value in byt_pin_config_set()
broxton:
- Switch to use Intel pin control PM ops
cannonlake:
- Switch to use Intel pin control PM ops
cedarfork:
- Switch to use Intel pin control PM ops
denverton:
- Switch to use Intel pin control PM ops
elkhartlake:
- Switch to use Intel pin control PM ops
emmitsburg:
- Switch to use Intel pin control PM ops
geminilake:
- Switch to use Intel pin control PM ops
icelake:
- Switch to use Intel pin control PM ops
intel:
- Add Intel Meteor Point pin controller and GPIO support
- use the correct _PM_OPS() export macro
- Add a generic Intel pin control platform driver
- Revert "Unexport intel_pinctrl_probe()"
- allow independent COMPILE_TEST
- Refactor intel_pinctrl_get_soc_data()
- Move default strength assignment to a switch-case
- Make PM ops functions static
- Provide Intel pin control wide PM ops structure
jasperlake:
- Switch to use Intel pin control PM ops
lakefield:
- Switch to use Intel pin control PM ops
lewisburg:
- Switch to use Intel pin control PM ops
lynxpoint:
- Simplify code with cleanup helpers
meteorlake:
- Switch to use Intel pin control PM ops
sunrisepoint:
- Switch to use Intel pin control PM ops
tangier:
- simplify locking using cleanup helpers
- Move default strength assignment to a switch-case
- Enable 910 Ohm bias
tigerlake:
- Switch to use Intel pin control PM ops
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This driver supports pinctrl/GPIO hardware found on Intel Meteor Point
(a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces
including GPIO interrupts.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Use macros defined in linux/cleanup.h to automate resource lifetime
control in the driver.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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When ->pin_config_set() is called from the GPIO library (assumed
GpioIo() ACPI resource), the argument can be 1, when, for example,
PullDefault is provided. In such case we supply sane default in
the driver. Move that default assingment to a switch-case, so
it will be consolidated in one place.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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There is a piece of code that it being used at least twice.
Factor it out.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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When unpacked, the config value is split to two of different types.
Fix the types accordingly.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Use macros defined in linux/cleanup.h to automate resource lifetime
control in the driver.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Use lock guards from cleanup.h to simplify locking.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Since we don't have runtime PM handles here, we should be using
EXPORT_NS_GPL_DEV_SLEEP_PM_OPS() macro, so that the compiler can
discard it in case CONFIG_PM_SLEEP=n.
Fixes: b10a74b5c0c1 ("pinctrl: intel: Provide Intel pin control wide PM ops structure")
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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New generations of Intel platforms will provide better description
of the pin control devices in the ACPI tables. Hence, we may provide
a generic pin control platform driver to cover all of them. Currently
the following Intel SoCs / platforms require this to be functional:
- Lunar Lake
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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In order to prepare for a new coming driver export the original
intel_pinctrl_probe() again.
This reverts commit 0dd519e3784b13befa1cdfeff847a0885b06650f.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Now that we have completed the transition to standard ACPI helpers for the
entire Intel pinctrl tree, we can detach COMPILE_TEST from ACPI dependency.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Refactor intel_pinctrl_get_soc_data() to drop initial assignment
of the data variable. It's only used in ACPI case and instead
we may always assign it there as the ACPI ID table has the terminator
entry that has driver data set to NULL.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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iWhen ->pin_config_set() is called from the GPIO library (assumed
GpioIo() ACPI resource), the argument can be 1, when, for example,
PullDefault is provided. In such case we supply sane default in
the driver. Move that default assingment to a switch-case, so
it will be consolidated in one place.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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iWhen ->pin_config_set() is called from the GPIO library (assumed
GpioIo() ACPI resource), the argument can be 1, when, for example,
PullDefault is provided. In such case we supply sane default in
the driver. Move that default assingment to a switch-case, so
it will be consolidated in one place.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Family 7 (I2C) supports special bias value, i.e. 910 Ohm.
Enable it for configuring pin.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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No more users outside of the main module.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-18-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-17-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-16-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-15-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-14-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-13-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-12-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-11-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-10-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-9-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-8-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-7-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-5-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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With the help of EXPORT_NS_GPL_DEV_PM_OPS() and
NOIRQ_SYSTEM_SLEEP_PM_OPS() we may convert PM ops functions to become
static. This also takes into account the PM configuration options such
as CONFIG_PM and CONFIG_PM_SLEEP. Hence the first step is to provide
a generic PM ops structure that can be used by drivers directly.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231030120734.2831419-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.8
1. New hardware: Add pin controllers for Samsung ExynosAutov920 and
Google Tensor GS101.
2. Few DT bindings cleanups: add specific compatibles for each device
using generic compatible as fallback. This affects only DTS, no
driver changes are needed.
3. Allow setting affinity on non wake-up external GPIO interrupts.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pinctrl data for ExynosAutov920 SoC.
It has a newly applied pinctrl register layer for ExynosAuto series.
Pinctrl data for ExynosAutoV920 SoC.
- GPA0,GPA1 (10): External wake up interrupt
- GPQ0 (2): SPMI (PMIC I/F)
- GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio
- GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet
- GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose
- GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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New ExynosAuto series GPIO have a different register structure.
In the existing Exynos series, EINT control register is enumerated after
a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET).
However, from ExynosAutov920 SoC, the register that controls EINT belongs
to each GPIO bank, and each GPIO bank has 0x1000 align.
This is a structure to protect the GPIO bank using S2MPU in VM environment,
and will only be applied in ExynosAuto series SoCs.
--------------------------------------------------------------
| Original Exynos | ExynosAuto |
|------------------------------------------------------------|
| 0x0 GPIO_CON | 0x0 GPIO_CON |
| 0x4 GPIO_DAT | 0x4 GPIO_DAT |
| 0x8 GPIO_PUD | 0x8 GPIO_PUD |
| 0xc GPIO_DRV | 0xc GPIO_DRV |
| 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN |
| 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN |
|----------------------------| 0x18 EINT_CON (per_bank) |
| ... | 0x1c EINT_FLTCON0 (per_bank) |
| ... | 0x20 EINT_FLTCON1 (per_bank) |
| ... | 0x24 EINT_MASK (per_bank) |
| ... | 0x28 EINT_PEND (per_bank) |
|----------------------------|-------------------------------|
| 0x700 EINT_CON (global) | ... |
| 0x800 EINT_FLTCON (global) | ... |
| 0x900 EINT_MASK (global) | ... |
| 0xa00 EINT_FEND (global) | ... |
--------------------------------------------------------------
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Link: https://lore.kernel.org/r/20231211114145.106255-2-jaewon02.kim@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add support for the pin-controller found on the gs101 SoC used in
Pixel 6 phones.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-10-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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To support affinity setting for non wake up external gpio interrupt, add
irq_set_affinity callback using irq number from pinctrl driver data.
Before this patch, changing the irq affinity of gpio interrupt is not
possible:
# cat /proc/irq/418/smp_affinity
3ff
# echo 00f > /proc/irq/418/smp_affinity
# cat /proc/irq/418/smp_affinity
3ff
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 ...
418: 3631 0 0 0 ...
With this patch applied, it's possible to change irq affinity of gpio
interrupt:
# cat /proc/irq/418/smp_affinity
3ff
# echo 00f > /proc/irq/418/smp_affinity
# cat /proc/irq/418/smp_affinity
00f
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 ...
418: 3893 201 181 188 ...
Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20231126094618.2545116-1-youngmin.nam@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.8 (take two)
- Add pinmux groups, power source, and input/output enable support for
Ethernet pins on RZ/G2L SoCs,
- Miscellaneous fixes and improvements.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with
input enable. Enable this functionality for these pins.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to
have the direction of the IO buffer set as output for Ethernet to work
properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have
the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN.
As the pins supporting output enable are SoC specific, and there is a
limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify
output enable capable port limits in the platform-based configuration
data structure, to ensure proper validation.
The OEN support has been intantiated for RZ/G3S at the moment.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports
setting the power source for Ethernet pins. Based on the interface b/w
the Ethernet controller and the Ethernet PHY, and on board design, a
specific power source needs to be selected. The GPIO controller
supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet
pins. This can be selected though the ETHx_POC registers (x={0, 1}).
Adjust the driver to support this, and to do proper instantiation for
the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been
tested at the moment.
While at it, as the power registers on RZ/G2L support access sizes of 8
bits, and these registers on RZ/G3S support access sizes of 8/16/32
bits, replace writel()/readl() on these registers with writeb()/readb().
This should allow us to use the same code on both SoCs w/o any issues.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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On RZ/G3S different Ethernet pins need to be configured with different
settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins
need output-enable). Adjust the driver to allow specifying pin
configuration for pinmux groups. With this, DT settings like the
following are taken into account by the driver:
eth0_pins: eth0 {
tx_ctl {
pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
};
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Move arg and index in the main block of the function as they are used by
more than one case block of switch-case (3 out of 4 for arg, 2 out of 4
for index). In this way some lines of code are removed.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Immutable tag for the PEF2256 framer
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