summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl (follow)
Commit message (Collapse)AuthorAgeFilesLines
* pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for nowStephan Gerhold2024-09-021-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On X1E80100, GPIO interrupts for wakeup-capable pins have been broken since the introduction of the pinctrl driver. This prevents keyboard and touchpad from working on most of the X1E laptops. So far we have worked around this by manually building a kernel with the "wakeup-parent" removed from the pinctrl node in the device tree, but we cannot expect all users to do that. Implement a similar workaround in the driver by clearing the wakeirq_map for X1E80100. This avoids using the PDC wakeup parent for all GPIOs and handles the interrupts directly in the pinctrl driver instead. The PDC driver needs additional changes to support X1E80100 properly. Adding a workaround separately first allows to land the necessary PDC changes through the normal release cycle, while still solving the more critical problem with keyboard and touchpad on the current stable kernel versions. Bypassing the PDC is enough for now, because we have not yet enabled the deep idle states where using the PDC becomes necessary. Cc: stable@vger.kernel.org Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/20240830-x1e80100-bypass-pdc-v1-1-d4c00be0c3e3@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pinsHuang-Huang Bao2024-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base iomux offsets for each GPIO pin line are accumulatively calculated based off iomux width flag in rockchip_pinctrl_get_soc_data. If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8 bytes, otherwise it would increase by 4 bytes. Despite most of GPIO2-B iomux have 2-bit data width, which can be fit into 4 bytes space with write mask, it actually take 8 bytes width for whole GPIO2-B line. Commit e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") wrongly set iomux width flag to 0, causing all base iomux offset for line after GPIO2-B to be calculated wrong. Fix the iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is correctly increased by 8, matching the actual width of GPIO2-B iomux. Fixes: e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") Cc: stable@vger.kernel.org Reported-by: Richard Kojedzinszky <richard@kojedz.in> Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@kojedz.in/ Tested-by: Richard Kojedzinszky <richard@kojedz.in> Signed-off-by: Huang-Huang Bao <i@eh5.me> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Trevor Woerner <twoerner@gmail.com> Link: https://lore.kernel.org/20240709105428.1176375-1-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: starfive: jh7110: Correct the level trigger configuration of iev ↵Hal Feng2024-08-231-2/+2
| | | | | | | | | | | register A mistake was made in level trigger register configuration. Correct it. Fixes: 447976ab62c5 ("pinctrl: starfive: Add StarFive JH7110 sys controller driver") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/20240812070108.100923-1-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: x1e80100: Fix special pin offsetsKonrad Dybcio2024-08-231-4/+4
| | | | | | | | | | | | | Remove the erroneus 0x100000 offset to prevent the boards from crashing on pin state setting, as well as for the intended state changes to take effect. Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver") Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20240809-topic-h_sdc-v1-1-bb421532c531@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: common-v2: Fix broken bias-disable for PULL_PU_PD_RSEL_TYPENícolas F. R. A. Prado2024-08-231-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Despite its name, commit fed74d75277d ("pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPE") actually broke bias-disable for PULL_PU_PD_RSEL_TYPE. mtk_pinconf_bias_set_combo() tries every bias method supported by the pin until one succeeds. For PULL_PU_PD_RSEL_TYPE pins, before the breaking commit, mtk_pinconf_bias_set_rsel() would be called first to try and set the RSEL value (as well as PU and PD), and if that failed, the only other valid option was that bias-disable was specified, which would then be handled by calling mtk_pinconf_bias_set_pu_pd() and disabling both PU and PD. The breaking commit misunderstood this logic and added an early "return 0" in mtk_pinconf_bias_set_rsel(). The result was that in the bias-disable case, the bias was left unchanged, since by returning success, mtk_pinconf_bias_set_combo() no longer tried calling mtk_pinconf_bias_set_pu_pd() to disable the bias. Since the logic for configuring bias-disable on PULL_PU_PD_RSEL_TYPE pins required mtk_pinconf_bias_set_rsel() to fail first, in that case, an error was printed to the log, eg: mt8195-pinctrl 10005000.pinctrl: Not support rsel value 0 Ohm for pin = 29 (GPIO29) This is what the breaking commit actually got rid of, and likely part of the reason why that commit was thought to be fixing functionality, while in reality it was breaking it. Instead of simply reverting that commit, restore the functionality but in a way that avoids the error from being printed and makes the code less confusing: * Return 0 explicitly if a bias method was successful * Introduce an extra function mtk_pinconf_bias_set_pu_pd_rsel() that calls both mtk_pinconf_bias_set_rsel() (only if needed) and mtk_pinconf_bias_set_pu_pd() * And analogously for the corresponding getters Fixes: fed74d75277d ("pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPE") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/20240808-mtk-rsel-bias-disable-fix-v1-1-1b4e85bf596c@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: single: fix potential NULL dereference in pcs_get_function()Ma Ke2024-08-231-0/+2
| | | | | | | | | | | | | | pinmux_generic_get_function() can return NULL and the pointer 'function' was dereferenced without checking against NULL. Add checking of pointer 'function' in pcs_get_function(). Found by code review. Cc: stable@vger.kernel.org Fixes: 571aec4df5b7 ("pinctrl: single: Use generic pinmux helpers for managing functions") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Link: https://lore.kernel.org/20240808041355.2766009-1-make24@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: make it work with current gpiolibThomas Blocher2024-08-231-1/+4
| | | | | | | | | | | | | | | | | | | | pinctrl-at91 currently does not support the gpio-groups devicetree property and has no pin-range. Because of this at91 gpios stopped working since patch commit 2ab73c6d8323fa1e ("gpio: Support GPIO controllers without pin-ranges") This was discussed in the patches commit fc328a7d1fcce263 ("gpio: Revert regression in sysfs-gpio (gpiolib.c)") commit 56e337f2cf132632 ("Revert "gpio: Revert regression in sysfs-gpio (gpiolib.c)"") As a workaround manually set pin-range via gpiochip_add_pin_range() until a) pinctrl-at91 is reworked to support devicetree gpio-groups b) another solution as mentioned in commit 56e337f2cf132632 ("Revert "gpio: Revert regression in sysfs-gpio (gpiolib.c)"") is found Signed-off-by: Thomas Blocher <thomas.blocher@ek-dev.de> Link: https://lore.kernel.org/5b992862-355d-f0de-cd3d-ff99e67a4ff1@ek-dev.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: x1e80100: Update PDC hwirq mapKonrad Dybcio2024-08-051-12/+15
| | | | | | | | | | | | | | | | | The current map seems to be out of sync (and includes a duplicate entry for GPIO193..). Replace it with the map present in shipping devices' ACPI tables. This new one seems more complete, as it e.g. contains GPIO145 (PCIE6a WAKE#) Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Link: https://lore.kernel.org/20240711-topic-x1e_pdc_tlmm-v1-1-e278b249d793@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* of: remove internal arguments from of_property_for_each_u32()Luca Ceresoli2024-07-252-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The of_property_for_each_u32() macro needs five parameters, two of which are primarily meant as internal variables for the macro itself (in the for() clause). Yet these two parameters are used by a few drivers, and this can be considered misuse or at least bad practice. Now that the kernel uses C11 to build, these two parameters can be avoided by declaring them internally, thus changing this pattern: struct property *prop; const __be32 *p; u32 val; of_property_for_each_u32(np, "xyz", prop, p, val) { ... } to this: u32 val; of_property_for_each_u32(np, "xyz", val) { ... } However two variables cannot be declared in the for clause even with C11, so declare one struct that contain the two variables we actually need. As the variables inside this struct are not meant to be used by users of this macro, give the struct instance the noticeable name "_it" so it is visible during code reviews, helping to avoid new code to use it directly. Most usages are trivially converted as they do not use those two parameters, as expected. The non-trivial cases are: - drivers/clk/clk.c, of_clk_get_parent_name(): easily doable anyway - drivers/clk/clk-si5351.c, si5351_dt_parse(): this is more complex as the checks had to be replicated in a different way, making code more verbose and somewhat uglier, but I refrained from a full rework to keep as much of the original code untouched having no hardware to test my changes All the changes have been build tested. The few for which I have the hardware have been runtime-tested too. Reviewed-by: Andre Przywara <andre.przywara@arm.com> # drivers/clk/sunxi/clk-simple-gates.c, drivers/clk/sunxi/clk-sun8i-bus-gates.c Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> # drivers/gpio/gpio-brcmstb.c Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> # drivers/irqchip/irq-atmel-aic-common.c Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # drivers/iio/adc/ti_am335x_adc.c Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> # drivers/pwm/pwm-samsung.c Acked-by: Richard Leitner <richard.leitner@linux.dev> # drivers/usb/misc/usb251xb.c Acked-by: Mark Brown <broonie@kernel.org> # sound/soc/codecs/arizona.c Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com> # sound/soc/codecs/arizona.c Acked-by: Michael Ellerman <mpe@ellerman.id.au> # arch/powerpc/sysdev/xive/spapr.c Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Acked-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20240724-of_property_for_each_u32-v3-1-bea82ce429e2@bootlin.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
* Merge tag 'pinctrl-v6.11-1' of ↵Linus Torvalds2024-07-2186-1666/+6040
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ...
| * Merge tag 'renesas-pinctrl-for-v6.11-tag3' of ↵Linus Walleij2024-07-051-49/+95
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.11 (take three) - Support output enable on RZ/G2L. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * pinctrl: renesas: rzg2l: Support output enable on RZ/G2LPaul Barker2024-07-041-4/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functionsPaul Barker2024-07-041-49/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variable naming in the various OEN functions has been confusing. We were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get() and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the oen_read() and oen_write() functions. This doesn't make sense, the first of these isn't actually an offset and the second is not needed for RZ/V2H but leads to confusion with the bit variable used within these functions. To tidy this up, instead pass the _pin variable directly to the oen_read() and oen_write() functions with consistent naming. Then rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port and pin numbers it needs. Instead of passing the pin capabilities into oen_read() and oen_write(), check that the pin supports OEN before calling these functions. Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give a single translation function which returns an error if the pin doesn't support OEN. While we're here, remove an unnecessary branch and clarify the variable naming. Lastly, check that we are not dealing with a dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-3-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Clarify OEN read/write supportPaul Barker2024-07-041-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently support OEN read/write for the RZ/G3S SoC but not the RZ/G2L SoC family (consisting of RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L & RZ/Five). The appropriate functions are renamed to clarify this and to match the callback names. We should also only set the oen_read and oen_write function pointers for the devices which support these operations. This requires us to check that these function pointers are valid before calling them. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-2-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: freescale: Use scope based of_node_put() cleanupsPeng Fan2024-07-033-39/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-4-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: equilibrium: Use scope based of_node_put() cleanupsPeng Fan2024-07-031-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-3-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ti: iodelay: Use scope based of_node_put() cleanupsPeng Fan2024-07-031-28/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-2-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32Alexey Klimov2024-07-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Account for more than only 23 GPIOs in LPASS Low Power Island pinctrl generic driver. The previous value 23 was chosen to satisfy existing SoC-specific drivers. However SM4250 LPI pinctrl uses more than 23 GPIOs and its probe routine fails on: if (WARN_ON(data->npins > MAX_NR_GPIO)) return -EINVAL; with the following message: [ 10.709014] ------------[ cut here ]------------ [ 10.719085] WARNING: CPU: 1 PID: 56 at drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:446 lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719108] Modules linked in: [...] [ 10.719238] CPU: 1 PID: 56 Comm: kworker/u33:0 Not tainted 6.10.0-rc2-00012-ge45ddb1f8d34-dirty #7 [ 10.719245] Hardware name: Qualcomm Technologies, Inc. QRB4210 RB2 (DT) [ 10.719250] Workqueue: events_unbound deferred_probe_work_func [ 10.719265] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 10.719271] pc : lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719278] lr : lpi_pinctrl_probe+0x44/0x388 [pinctrl_lpass_lpi] ... [ 10.719357] Call trace: [ 10.719361] lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719369] platform_probe+0x68/0xc4 [ 10.719378] really_probe+0xbc/0x29c [ 10.719384] __driver_probe_device+0x78/0x12c [ 10.719390] driver_probe_device+0xd8/0x15c [ 10.719395] __device_attach_driver+0xb8/0x134 [ 10.719401] bus_for_each_drv+0x88/0xe8 [ 10.719407] __device_attach+0xa0/0x190 [ 10.719412] device_initial_probe+0x14/0x20 [ 10.719418] bus_probe_device+0xac/0xb0 [ 10.719423] deferred_probe_work_func+0x88/0xc0 [ 10.719429] process_one_work+0x150/0x294 [ 10.719439] worker_thread+0x2f8/0x408 [ 10.719445] kthread+0x110/0x114 [ 10.719452] ret_from_fork+0x10/0x20 [ 10.719459] ---[ end trace 0000000000000000 ]--- [ 10.719589] qcom-sm4250-lpass-lpi-pinctrl a7c0000.pinctrl: probe with driver qcom-sm4250-lpass-lpi-pinctrl failed with error -22 Fixes: c2e5a25e8d88 ("pinctrl: qcom: Introduce SM4250 LPI pinctrl driver") Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20240627003654.242870-1-alexey.klimov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cy8c95x0: Update cache modificationPatrick Rudolph2024-07-031-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the previous review cycle the regmap cache update code was questioned since it seems and odd way of using regmap_update_bits(). Thus update the regmap cache modification code to better explain what it does and why it's done. This is no functional change, but it's improving code maintainability. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/20240626084525.787298-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cy8c95x0: Use cleanup.hPatrick Rudolph2024-07-031-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | Use the guard mutex from cleanup.h to make the code more readable. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/20240626084525.787298-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'renesas-pinctrl-for-v6.11-tag2-v2' of ↵Linus Walleij2024-07-024-418/+557
| |\| | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * pinctrl: renesas: r8a779h0: Remove unneeded separatorsGeert Uytterhoeven2024-07-011-21/+9
| | | | | | | | | | | | | | | | | | | | | | | | Usually there are no separators between alternate functions. Remove them to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/1fcd4f8734d063c9a691d9ab8ca0543892eb8388.1718378979.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and functionGeert Uytterhoeven2024-07-011-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9c33c36d13a5e38d79fa53085339b14631888b50.1718378943.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Remove unneeded separatorsGeert Uytterhoeven2024-07-011-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | Usually there are no separators between alternate functions. Remove them to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/2375711d5edd03a209b4ed996f136e1f3c649773.1718378859.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779h0: Add AVB MII pins and groupsGeert Uytterhoeven2024-07-011-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | EtherAVB instances 0 and 1 support both RGMII and MII interfaces. Add the missing pins and groups for MII. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/4a0a12227f2145ef53b18bc08f45b19dcd745fc6.1718378739.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix TPU suffixesGeert Uytterhoeven2024-07-011-65/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Timer Pulse Unit channels have two alternate pin groups: "tpu_to[0-3]" and "tpu_to[0-3]_a". Increase uniformity by adopting R-Car V4M naming: - Rename "tpu_to[0-3]_a" to "tpu_to[0-3]_b", - Rename "tpu_to[0-3]" to "tpu_to[0-3]_a", Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 85a9cbe4c57bb958 ("pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/0dd9428bc24e97e1001ed3976b1cb98966f5e7e3.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix TCLK suffixesGeert Uytterhoeven2024-07-011-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pins named both TCLK3 and TCLK4. To differentiate, the pin control driver uses "TCLK[34]" and "TCLK[34]_X". In addition, there are alternate pins without suffix, and with an "_A" or "_B" suffix. Increase uniformity by adopting R-Car V4M naming: - Rename "TCLK2_B" to "TCLK2_C", - Rename "TCLK[12]_A" to "TCLK[12]_B", - Rename "TCLK[12]" to "TCLK[12]_A", - Rename "TCLK[34]_A" to "TCLK[34]_C", - Rename "TCLK[34]_X" to "TCLK[34]_A", - Rename "TCLK[34]" to "TCLK[34]_B". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 0df46188a58895e1 ("pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_X") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/2845ff1f8fe1fd8d23d2f307ad5e8eb8243da608.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: FIX PWM suffixesGeert Uytterhoeven2024-07-011-40/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | PWM channels 0, 2, 8, and 9 do not have alternate pins. Remove their "_a" or "_b" suffixes to increase uniformity. Fixes: c606c2fde2330547 ("pinctrl: renesas: r8a779g0: Add missing PWM") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/abb748e6e1e4e7d78beac7d96e7a0a3481b32e75.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix IRQ suffixesGeert Uytterhoeven2024-07-011-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The suffixes of the IRQ identifiers for external interrupts 0-3 are inconsistent: - "IRQ0" and "IRQ0_A", - "IRQ1" and "IRQ1_A", - "IRQ2" and "IRQ2_A", - "IRQ3" and "IRQ3_B". The suffixes for external interrupts 4 and 5 do follow conventional naming: - "IRQ4A" and IRQ4_B", - "IRQ5". Fix this by adopting R-Car V4M naming: - Rename "IRQ[0-2]_A" to "IRQ[0-2]_B", - Rename "IRQ[0-3]" to "IRQ[0-3]_A". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 1b23d8a478bea9d1 ("pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/8ce9baf0a0f9346544a3ac801fd962c7c12fd247.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix (H)SCIF3 suffixesGeert Uytterhoeven2024-07-011-98/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (H)SCIF instance 3 has two alternate pin groups: "hscif3" and "hscif3_a", resp. "scif3" and "scif3_a", but the actual meanings of the pins within the groups do not match. Increase uniformity by adopting R-Car V4M naming: - Rename "hscif3_a" to "hscif3_b", - Rename "hscif3" to "hscif3_a", - Rename "scif3" to "scif3_b". While at it, remove unneeded separators. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 213b713255defaa6 ("pinctrl: renesas: r8a779g0: Add missing HSCIF3_A") Fixes: 49e4697656bdd1cd ("pinctrl: renesas: r8a779g0: Add missing SCIF3") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/61fdde58e369e8070ffd3c5811c089e6219c7ecc.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix (H)SCIF1 suffixesGeert Uytterhoeven2024-07-011-106/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pin groups (GP0_14-18 and GP1_6-10) each named both HSCIF1 and SCIF1. To differentiate, the pin control driver uses "(h)scif1" and "(h)scif1_x", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "(h)scif1" to "(h)scif1_a", - Rename "(h)scif1_x" to "(h)scif1_b". Adopt the R-Car V4M naming "(h)scif1_a" and "(h)scif1_b" to increase uniformity. While at it, remove unneeded separators. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: cf4f7891847bc558 ("pinctrl: renesas: r8a779g0: Add missing HSCIF1_X") Fixes: 9c151c2be92becf2 ("pinctrl: renesas: r8a779g0: Add missing SCIF1_X") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/5009130d1867e12abf9b231c8838fd05e2b28bee.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix FXR_TXEN[AB] suffixesGeert Uytterhoeven2024-07-011-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pins named both "FXR_TXEN[AB]". To differentiate, the pin control driver uses "FXR_TXEN[AB]" and "FXR_TXEN[AB]_X", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "FXR_TXEN[AB]" to "FXR_TXEN[AB]_A", - Rename "FXR_TXEN[AB]_X" to "FXR_TXEN[AB]_B". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 1c2646b5cebfff07 ("pinctrl: renesas: r8a779g0: Add missing FlexRay") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/5e1e9abb46c311d4c54450d991072d6d0e66f14c.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Fix CANFD5 suffixGeert Uytterhoeven2024-07-011-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAN-FD instance 5 has two alternate pin groups: "canfd5" and "canfd5_b". Rename the former to "canfd5_a" to increase uniformity. While at it, remove the unneeded separator. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: c2b4b2cd632d17e7 ("pinctrl: renesas: r8a779g0: Add missing CANFD5_B") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/10b22d54086ed11cdfeb0004583029ccf249bdb9.1717754960.git.geert+renesas@glider.be
| | * pinctrl: renesas: sh73a0: Use rdev_get_drvdata()Michał Mirosław2024-07-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace `reg_data` access with the official wrapper. The field is going away soon. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/bb6b85722d80d665779e3043d1499c4fc38f0ff3.1714562004.git.mirq-linux@rere.qmqm.pl Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Reorganize variable configuration macroLad Prabhakar2024-06-241-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin but served as a flag indicating that the pins of a port have different capabilities. To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside `RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally, introduce new macros for packing variable port configurations: - `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations for a packed port. - `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle variable pin configurations for a sparse port. Due to the above change the configuration macros have been reorganized as follows: - Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`, `PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one to accommodate the removal of `PIN_CFG_VARIABLE`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the fileLad Prabhakar2024-06-241-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for dedicated pins for improved readability. While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place it just above the macro for clarity. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62)Lad Prabhakar2024-06-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`, to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`. Previously, these bit masks were placed higher up in the bit range, which did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any conflicts. The updated masks are now: - `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`) - `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`) Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wideLad Prabhakar2024-06-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: mlxbf3: Fix return value check for devm_platform_ioremap_resourceChen Ni2024-06-261-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix return value check for devm_platform_ioremap_resource() in mlxbf3_pinctrl_probe(). Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Acked-by: Asmaa Mnebhi <asmaa@nvidia.com> Link: https://lore.kernel.org/20240621091637.2299310-1-nichen@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: aspeed-g6: Add NCSI pin group configPotin Lai2024-06-261-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO, reducing the number of required pins. LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: Introduce SM4250 LPI pinctrl driverSrinivas Kandagatla2024-06-263-0/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: k210: Use scope based of_node_put() cleanupsPeng Fan2024-06-261-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-19-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: freescale: mxs: Fix refcount of childPeng Fan2024-06-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_get_next_child() will increase refcount of the returned node, need use of_node_put() on it when done. Per current implementation, 'child' will be override by for_each_child_of_node(np, child), so use of_get_child_count to avoid refcount leakage. Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-18-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinconf-generic: Use scope based of_node_put() cleanupsPeng Fan2024-06-261-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-17-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: bcm63xx: Use scope based of_node_put() cleanupsPeng Fan2024-06-261-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-16-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: Use scope based of_node_put() cleanupsPeng Fan2024-06-262-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-14-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: Use scope based of_node_put() cleanupsPeng Fan2024-06-262-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-13-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: s32cc: Use scope based of_node_put() cleanupsPeng Fan2024-06-261-21/+10
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-12-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: at91: Use scope based of_node_put() cleanupsPeng Fan2024-06-262-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-11-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: rockchip: Use scope based of_node_put() cleanupsPeng Fan2024-06-261-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-9-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 20:18:05 +0100