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* Merge tag 'pinctrl-v6.4-1' of ↵Linus Torvalds2023-05-03102-9356/+6810
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Mostly drivers! Nothing special: some new Qualcomm chips as usual, and the new NXP S32 and nVidia BlueField-3. Core changes: - Make a lot of pin controllers with GPIO and irqchips immutable, i.e. not living structs, but const structs. This is driving a changed initiated by the irqchip maintainers. New drivers: - New driver for the NXP S32 SoC pin controller - As part of a thorough cleanup and restructuring of the Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were folded into the Mediatek directory and the family is renamed "mtmips". The Ralink chips live on as Mediatek MIPS family where new variants can be added. As part of this work also the device tree bindings were reworked. - New subdriver for the Qualcomm SM7150 SoC. - New subdriver for the Qualcomm IPQ9574 SoC. - New driver for the nVidia BlueField-3 SoC. - Support for the Qualcomm PMM8654AU mixed signal circuit GPIO. - Support for the Qualcomm PMI632 mixed signal circuit GPIO. Improvements: - Add some missing pins and generic cleanups on the Renesas r8a779g0 and r8a779g0 pin controllers. Generic Renesas extension for power source selection on several SoCs. - Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers - Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver. - Several device tree binding cleanups as the binding YAML syntax is solidifying" * tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits) pinctrl-bcm2835.c: fix race condition when setting gpio dir dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2" dt-bindings: pinctrl: qcom: Add few missing functions pinctrl: qcom: spmi-gpio: Add PMI632 support dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632 pinctrl: wpcm450: select MFD_SYSCON pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip pinctrl: qcom spmi-mpp: Convert to immutable irq_chip pinctrl: plgpio: Convert to immutable irq_chip pinctrl: pistachio: Convert to immutable irq_chip pinctrl: pic32: Convert to immutable irq_chip pinctrl: sx150x: Convert to immutable irq_chip pinctrl: stmfx: Convert to immutable irq_chip pinctrl: st: Convert to immutable irq_chip pinctrl: mcp23s08: Convert to immutable irq_chip pinctrl: equilibrium: Convert to immutable irq_chip pinctrl: npcm7xx: Convert to immutable irq_chip pinctrl: armada-37xx: Convert to immutable irq_chip pinctrl: nsp: Convert to immutable irq_chip ...
| * pinctrl-bcm2835.c: fix race condition when setting gpio dirHans Verkuil2023-04-211-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past setting the pin direction called pinctrl_gpio_direction() which uses a mutex to serialize this. That was changed to set the direction directly in the pin controller driver, but that lost the serialization mechanism. Since the direction of multiple pins are in the same register you can have a race condition, something that was in fact observed with the cec-gpio driver. Add a new spinlock to serialize writing to the FSEL registers. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Fixes: 1a4541b68e25 ("pinctrl-bcm2835: don't call pinctrl_gpio_direction()") Link: https://lore.kernel.org/r/4302b66b-ca20-0f19-d2aa-ee8661118863@xs4all.nl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Add PMI632 supportLuca Weiss2023-04-211-0/+1
| | | | | | | | | | | | | | | | | | Add support for the 8 GPIOs found on PMI632. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230414-pmi632-v2-2-98bafa909c36@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: wpcm450: select MFD_SYSCONJonathan Neuschäfer2023-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | The pinctrl-wpcm450 driver relies on MFD_SYSCON functionality in order to find some of its MMIO registers. Select MFD_SYSCON from PINCTRL_WPCM450 to ensure that it's enabled. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20230412185049.3782842-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom ssbi-gpio: Convert to immutable irq_chipLinus Walleij2023-04-201-3/+21
| | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-6-6b59a5186b00@linaro.org
| * pinctrl: qcom ssbi-mpp: Convert to immutable irq_chipLinus Walleij2023-04-201-8/+27
| | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-5-6b59a5186b00@linaro.org
| * pinctrl: qcom spmi-mpp: Convert to immutable irq_chipLinus Walleij2023-04-201-10/+28
| | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-4-6b59a5186b00@linaro.org
| * pinctrl: plgpio: Convert to immutable irq_chipLinus Walleij2023-04-201-2/+6
| | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-3-6b59a5186b00@linaro.org
| * pinctrl: pistachio: Convert to immutable irq_chipLinus Walleij2023-04-201-10/+25
| | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-2-6b59a5186b00@linaro.org
| * pinctrl: pic32: Convert to immutable irq_chipLinus Walleij2023-04-201-11/+25
| | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Switch some call to use irqd_to_hwirq() in the process. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-1-6b59a5186b00@linaro.org
| * pinctrl: sx150x: Convert to immutable irq_chipLinus Walleij2023-04-141-27/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. I switched to consistently using irqd_to_hwirq() consistently while we are at it. As the driver now needs to get the gpio_chip in the .irq_mask and .irq_unmask callbacks, I switched to a pattern where we first fetch the gpio_chip and then the state container from that in two steps. The compiler will do the same thing anyway. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-9-503788a7f6e6@linaro.org
| * pinctrl: stmfx: Convert to immutable irq_chipLinus Walleij2023-04-141-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. This driver rolls it's own resource handling and does not use GPIOCHIP_IRQ_RESOURCE_HELPERS. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-8-503788a7f6e6@linaro.org
| * pinctrl: st: Convert to immutable irq_chipLinus Walleij2023-04-141-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. I switched to using irqd_to_hwirq() consistently while we are at it. This driver does not use the GPIOCHIP_IRQ_RESOURCE_HELPERS as it defines its own resource reservations, simply in order to turn IRQ lines into inputs on initialization. Also switched the open coded calls to gpiochip_lock_as_irq() to gpiochip_reqres_irq() so we also get the right module reference counting. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-7-503788a7f6e6@linaro.org
| * pinctrl: mcp23s08: Convert to immutable irq_chipLinus Walleij2023-04-142-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. I switched to using irqd_to_hwirq() consistently while we are at it. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-6-503788a7f6e6@linaro.org
| * pinctrl: equilibrium: Convert to immutable irq_chipLinus Walleij2023-04-142-10/+14
| | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-5-503788a7f6e6@linaro.org
| * pinctrl: npcm7xx: Convert to immutable irq_chipLinus Walleij2023-04-141-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. I refactored the way the state container was accessed in the irq_chip callbacks to all look the same and switch to use irqd_to_hwirq() while we are at it. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-4-503788a7f6e6@linaro.org
| * pinctrl: armada-37xx: Convert to immutable irq_chipLinus Walleij2023-04-141-10/+24
| | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-3-503788a7f6e6@linaro.org
| * pinctrl: nsp: Convert to immutable irq_chipLinus Walleij2023-04-141-10/+13
| | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-2-503788a7f6e6@linaro.org
| * pinctrl: iproc: Convert to immutable irq_chipLinus Walleij2023-04-141-13/+25
| | | | | | | | | | | | | | | | | | Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-1-503788a7f6e6@linaro.org
| * Merge tag 'renesas-pinctrl-for-v6.4-tag2' of ↵Linus Walleij2023-04-1138-225/+725
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.4 (take two) - Retain POCCTRL0 register across s2ram on R-Car D3, - Add support for Ethernet power-sources on R-Car V3M, V3H, E3, D3, and V4H, - Annotate sentinels in tables, - Add bias pinconf support and PWM pin groups on R-Car H1, - Miscellaneous fixes and improvements.
| | * pinctrl: renesas: core: Drop unneeded #ifdef CONFIG_OFGeert Uytterhoeven2023-03-301-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the of_node member of struct device always exists, and there is a dummy of of_device_get_match_data() for the !CONFIG_OF case, there is no longer a need to protect code using these interfaces with an #ifdef. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/55d72ce46b43ec2f41681cb5ba7ca7fcebdb98d1.1679416005.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a7779: Add PWM pins, groups, and functionsGeert Uytterhoeven2023-03-301-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for the PWM Timers on the Renesas R-Car H1 (R8A7779) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cea9723e9c3df4b1408750caa38886aac1fab5f7.1679329090.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a7779: Add bias pinconf supportGeert Uytterhoeven2023-03-301-7/+328
| | | | | | | | | | | | | | | | | | | | | | | | Implement support for pull-up handling for the R-Car H1 SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dd966cfc916ef881051ec53bc3393dce7eea8e03.1679328215.git.geert+renesas@glider.be
| | * pinctrl: renesas: Annotate sentinels in tablesGeert Uytterhoeven2023-03-3036-80/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Hence drop all such commas. Add comments to clarify the purpose of the empty elements. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/845f1d8285dd44522af1b0f429d4c6bd4759eb9e.1678272180.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sourcesGeert Uytterhoeven2023-03-301-9/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring the I/O voltage levels of the Ethernet AVB and Ethernet TSN pins on the R-Car V4H SoC. "PIN_VDDQ_AVB[012]" and "PIN_VDDQ_TSN0" can be configured for 1.8V or 2.5V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c046e0be7d26302061d7aa629180a451734ddf8f.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a77995: Add support for AVB power-sourceGeert Uytterhoeven2023-03-301-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car D3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f9164487715d8a4898ca651038c0b4d5013764c.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a77990: Add support for AVB power-sourceGeert Uytterhoeven2023-03-301-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car E3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/57883cd2d94c7919dc0f0db07cf6169ca89538e6.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a77980: Add support for AVB/GE power-sourcesGeert Uytterhoeven2023-03-301-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring the I/O voltage levels of the Ethernet AVB and Gigabit Ethernet pins on the R-Car V3H SoC. "PIN_VDDQ_AVB" and "PIN_VDDQ_GE" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3c26c4f3735a6d071685c507c065172e63af5d70.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a77970: Add support for AVB power-sourceGeert Uytterhoeven2023-03-301-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car V3M SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/eb4db82bdeb67507a1a77f63b9d90280d6f38ba4.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levelsGeert Uytterhoeven2023-03-303-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the Renesas pin control driver supports pins that can switch their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. However, some SoCs have pins that can switch between 1.8V and 2.5V. Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE capability and voltage level flags by a 2-bit field, to cover three possible I/O voltage switching options. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flagGeert Uytterhoeven2023-03-3011-63/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 537db25ca330dce0 ("pinctrl: renesas: Add I/O voltage level flag") introduced new flags to support pins that can switch their voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. The old SH_PFC_PIN_CFG_IO_VOLTAGE flag was retained to avoid having to change existing drivers. Replace SH_PFC_PIN_CFG_IO_VOLTAGE by SH_PFC_PIN_CFG_IO_VOLTAGE_18_33, to make the voltage configuration explicit, and to prepare for the advent of support for more voltage levels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ae5f879c093f3e3cd50ba1495975bccfad81237b.1678271030.git.geert+renesas@glider.be
| | * pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resumeGeert Uytterhoeven2023-03-301-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The POC Control Register 0 (POCCTRL0) on R-Car D3 is not registered in the pinmux_ioctrl_regs[] array. Hence it is not saved/restored during suspend/resume, and its contents may be lost after s2ram. This went unnoticed when improving suspend/resume support in commit d92ee9cf8ec8d7fe ("pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume"). Fix this by moving the pinmux_ioctrl_regs[] array up, and adding the POCCTRL0 register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d17402b83b1f3fa0f572527c0382027bccb86205.1678271030.git.geert+renesas@glider.be
| * | pinctrl: qcom: Add "and" to PIN_CONFIG_INPUT_ENABLE commentDouglas Anderson2023-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment recently added talking about PIN_CONFIG_INPUT_ENABLE is clearly missing the word "and". Comments live forever, so let's fix it. Fixes: e49eabe3e13f ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE") Reported-by: Stephen Boyd <swboyd@chromium.org> Link: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4409769/comment/9a1d5def_e1e71db7/ Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230407142859.1.Ia5d70e320b60d6707c6182879097708e49b8b519@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-gpio: add support for pmm8654au-gpioBartosz Golaszewski2023-04-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the GPIO controller present on the pmm8654au PMIC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230327125316.210812-14-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mlxbf3: set varaiable mlxbf3_pmx_funcs storage-class-specifier to ↵Tom Rix2023-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | static smatch reports drivers/pinctrl/pinctrl-mlxbf3.c:162:20: warning: symbol 'mlxbf3_pmx_funcs' was not declared. Should it be static? This variable is only used in one file so it should be static. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230404004501.1913144-1-trix@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: Remove Intel Thunder Bay pinctrl driverLakshmi Sowjanya D2023-04-043-1314/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Link: https://lore.kernel.org/r/20230403120235.939-1-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: xway: drop the deprecated compatible stringsAleksander Jan Bajkowski2023-03-311-252/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code are marked as deprecated since kernel 4.5[1]. Downstream OpenWRT and upstream switched to the new string compatible 7 years ago. The old compatible strings can safely be dropped. [1] commit be14811c03cf ("pinctrl/lantiq: introduce new dedicated devicetree bindings") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Link: https://lore.kernel.org/r/20230330212225.10214-1-olek2@wp.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: amd: Add fields for interrupt status and wake statusMario Limonciello2023-03-311-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the firmware has misconfigured a GPIO it may cause interrupt status or wake status bits to be set and not asserted. Add these to debug output to catch this case. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230328174231.8924-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: amd: Adjust debugfs outputMario Limonciello2023-03-311-46/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More fields are to be added, so to keep the display from being too busy, adjust it. 1) Add a header to all columns 2) Except for interrupt, when fields have no data show empty 3) Remove otherwise blank whitespace Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230328174231.8924-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mcp23s08: Implement gpio bulk functionsUwe Kleine-König2023-03-291-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | To speed up some usecases implement reading and writing several IO lines at once. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230324164957.485924-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mcp23s08: Rename and change function that wraps regmap_update_bits()Uwe Kleine-König2023-03-291-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantic of mcp_set_mask() was surprising to me when I first read that driver. So it was unexpected that in the call mcp_set_mask(mcp, MCP_OLAT, mask, value); value was a bool. Make the function a thinner wrapper around regmap_update_bits() and rename it to also have a similar name. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230324164957.485924-2-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge branch 'ib-qcom-quad-spi' into develLinus Walleij2023-03-291-5/+31
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| * | | pinctrl: s32cc: Use generic struct data to describe pin functionChester Lin2023-03-272-20/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace struct s32_pmx_func with generic struct pinfunction since they have the same data fields. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-5-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: s32cc: embed generic struct pingroupChester Lin2023-03-272-36/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use generic data structure to describe pin control groups in S32 SoC family and drop duplicated struct members. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-4-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: s32cc: refactor pin config parsingChester Lin2023-03-271-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move common codes into smaller inline functions and remove argument checks that are not actually used by pull up/down bits in the S32 MSCR register. Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-3-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: s32: refine error/return/config checks and simplify driver codesChester Lin2023-03-272-69/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve error/return code handlings and config checks in order to have better reliability and simplify driver codes such as removing/changing improper macros, blanks, print formats and helper calls. Signed-off-by: Chester Lin <clin@suse.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230327062754.3326-2-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'renesas-pinctrl-for-v6.4-tag1' of ↵Linus Walleij2023-03-279-6513/+565
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.4 - Add pin groups for audio on R-Car V4H, - Drop support for the obsolete R-Car H3 ES1.* (R8A77950) SoC, - Miscellaneous fixes and improvements.
| | * | pinctrl: renesas: Drop support for Renesas-specific propertiesGeert Uytterhoeven2023-03-161-26/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last user of the Renesas-specific properties was converted to the standard properties in commit af897250ea54c6f2 ("ARM: dts: gose: use generic pinctrl properties in SDHI nodes") in v4.10. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/ff9c14781110bbf19b56b45dd1f01e6da90319ad.1678704441.git.geert+renesas@glider.be
| | * | pinctrl: renesas: Remove R-Car H3 ES1.* handlingWolfram Sang2023-03-105-5992/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230307105645.5285-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: r8a779g0: Fix ERROROUTC function namesGeert Uytterhoeven2023-03-101-251/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, the ERROROUTC signal is active-low. Hence add the missing "_N" suffix to the pin function's names. Resize column 2 of all IPxSR* definitions to accomodate the longer names. Fixes: b811062e5fd0343c ("pinctrl: renesas: r8a779g0: Add missing ERROROUTC_A") Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1774303989e7d61f08fa81f1c2fa1b394505645f.1669036423.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-07 12:35:51 +0100