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* Merge tag 'pwm/for-4.14-rc1' of ↵Linus Torvalds2017-09-1115-301/+660
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "The changes for this release include a new driver for the PWM controller found on SoCs of the ZTX ZX family. Support for an old SH-Mobile SoC has been dropped and the Rockchip and MediaTek drivers gain support for more generations. Other than that there are a bunch of coding style fixes, minor bug fixes and cleanup as well as documentation patches" * tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (32 commits) pwm: pwm-samsung: fix suspend/resume support pwm: samsung: Remove redundant checks from pwm_samsung_config() pwm: mediatek: Disable clock on PWM configuration failure dt-bindings: pwm: Add MT2712/MT7622 information pwm: mediatek: Fix clock control issue pwm: mediatek: Fix PWM source clock selection pwm: mediatek: Fix Kconfig description pwm: tegra: Explicitly request exclusive reset control pwm: hibvt: Explicitly request exclusive reset control pwm: tiehrpwm: Set driver data before runtime PM enable pwm: tiehrpwm: Miscellaneous coding style fixups pwm: tiecap: Set driver data before runtime PM enable pwm: tiecap: Miscellaneous coding style fixups dt-bindings: pwm: tiecap: Add TI 66AK2G SoC specific compatible pwm: tiehrpwm: fix clock imbalance in probe error path pwm: tiehrpwm: Fix runtime PM imbalance at unbind pwm: Kconfig: Enable pwm-tiecap to be built for Keystone pwm: Add ZTE ZX PWM device driver dt-bindings: pwm: Add bindings doc for ZTE ZX PWM controller pwm: bcm2835: Support for polarity setting via DT ...
| * pwm: pwm-samsung: fix suspend/resume supportBartlomiej Zolnierkiewicz2017-08-211-32/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix suspend/resume support: - add disabled_mask to struct samsung_pwm_chip to track PWM disabled state information in pwm_samsung_{disable,enable}() - rename pwm_samsung_config() to __pwm_samsung_config() and add extra force_period parameter to be used during resume (to force tin_ns and tcnt recalculation) - add pwm_samsung_config() wrapper for preserving old behavior - properly restore PWM configuration in pwm_samsung_resume() - remove no longer needed pwm_samsung_suspend() - update Copyrights Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: samsung: Remove redundant checks from pwm_samsung_config()Bartlomiej Zolnierkiewicz2017-08-211-3/+0
| | | | | | | | | | | | | | | | | | | | If the requested period_ns and duty_ns values are identical to the last programmed ones pwm_samsung_config() returns early and skips the hardware configuration. The same checks are now done by the PWM core so the driver specific ones can be removed. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Disable clock on PWM configuration failureZhi Mao2017-08-211-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | Make sure to disable the PWM clock if the PWM cannot be configured due to the clock divider exceeding the maximum value. While at it, replace the hardcoded maximum clock divider with a defined constant to improve code readability. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Fix clock control issueZhi Mao2017-08-211-22/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to save some power, do not prepare the top and main clocks during mtk_pwm_probe(). Instead, prepare the clocks only when necessary and also make sure to enable the clocks to match the semantics of the common clock framework. While at it, don't explicitly disable all PWM channels in ->remove() because all users should have done that already. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Fix PWM source clock selectionZhi Mao2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | In original code, the PWM output frequency is not correct when set bit<3>=1 to PWMCON register. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Fix Kconfig descriptionZhi Mao2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | Fix a copy/paste error that sneaked into the Kconfig description of the Mediatek PWM driver. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Explicitly request exclusive reset controlPhilipp Zabel2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: hibvt: Explicitly request exclusive reset controlPhilipp Zabel2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: linux-pwm@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiehrpwm: Set driver data before runtime PM enableThierry Reding2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | Runtime PM callbacks can be run right after runtime PM is enabled, so make sure to set the driver data before that. This is unlikely to ever happen with the current driver, but it doesn't hurt to follow best practices anyway. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiehrpwm: Miscellaneous coding style fixupsThierry Reding2017-08-211-50/+62
| | | | | | | | | | | | | | | | I noticed most of these while reviewing another patch and thought I'd fix them while at it. These are mostly changes to make variable types more strict and whitespace fixups. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiecap: Set driver data before runtime PM enableThierry Reding2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | Runtime PM callbacks can be run right after runtime PM is enabled, so make sure to set the driver data before that. This is unlikely to ever happen with the current driver, but it doesn't hurt to follow best practices anyway. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiecap: Miscellaneous coding style fixupsThierry Reding2017-08-211-41/+47
| | | | | | | | | | | | | | | | I noticed most of these while reviewing another patch and thought I'd fix them while at it. These are mostly changes to make variable types more strict and whitespace fixups. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiehrpwm: fix clock imbalance in probe error pathJohan Hovold2017-08-211-1/+6
| | | | | | | | | | | | | | | | Make sure to unprepare the clock before returning on late probe errors. Fixes: b388f15fd14c ("pwm: pwm-tiehrpwm: Use clk_enable/disable instead clk_prepare/unprepare.") Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tiehrpwm: Fix runtime PM imbalance at unbindJohan Hovold2017-08-211-1/+0
| | | | | | | | | | | | | | | | | | Remove unbalanced RPM put at driver unbind which resulted in a negative usage count. Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM") Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: Kconfig: Enable pwm-tiecap to be built for KeystoneVignesh R2017-08-211-1/+1
| | | | | | | | | | | | | | | | | | 66AK2G SoC has ECAP subsystem that is used as pwm-backlight provider for display. Hence, enable pwm-tiecap driver to be built for Keystone architecture. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: Add ZTE ZX PWM device driverShawn Guo2017-08-213-0/+292
| | | | | | | | | | | | | | | | | | | | | | It adds PWM device driver for ZTE ZX family SoCs. The PWM controller supports 4 devices with polarity configuration. The driver has been tested with pwm-regulator support to scale core voltage via cpufreq. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: bcm2835: Support for polarity setting via DTStefan Wahren2017-08-211-0/+2
| | | | | | | | | | | | | | | | | | This adds support for the third (optional) pwm cell to specify the polarity, which is needed by display backlights for example. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Add rk3328 supportDavid Wu2017-08-181-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The rk3328 SoC supports atomic update, we could lock the configuration of period and duty at first, after unlock is configured, the period and duty are effective at the same time. If the polarity, period and duty need to be configured together, the way for atomic update is "configure lock and old polarity" -> "configure period and duty" -> "configure unlock and new polarity". Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Use same PWM ops for each IPDavid Wu2017-08-181-111/+38
| | | | | | | | | | | | | | | | | | Just use the same PWM ops for each IP, and get rid of the ops in struct rockchip_pwm_data, but still define the three different instances of the struct to use common interface for each IP. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Move the configuration of polarityDavid Wu2017-08-181-24/+24
| | | | | | | | | | | | | | | | | | | | It is usually possible to configure the polarity, cycle and duty all at once, so that the polarity and cycle and duty are applied atomically. Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as well as prepare for the next atomic update commit. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Use pwm_apply() instead of pwm_enable()David Wu2017-08-181-63/+78
| | | | | | | | | | | | | | | | Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and pwm_apply_v2() instead. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Remove the judge from return value of pwm_config()David Wu2017-08-181-10/+2
| | | | | | | | | | | | | | | | | | It seems the rockchip_pwm_config() always returns the result 0, so remove the judge. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: rockchip: Add APB and function both clocks supportDavid Wu2017-08-181-9/+49
| | | | | | | | | | | | | | | | | | New PWM module provides two individual clocks for APB clock and function clock. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: renesas-tpu: Remove support for SH7372Simon Horman2017-08-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu driver. Commit edf4100906044225 ("ARM: shmobile: sh7372 dtsi: Remove Legacy file") removed this SoC from the kernel in v4.1. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: vt8500: Undo preparation of a clock source.Arvind Yadav2017-07-251-0/+1
| | | | | | | | | | | | | | | | Undo preparation of a clock source if vt8500_pwm_probe() is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: pca9685: clarify pca9685_set_sleep_mode() interface.Sven Van Asbroeck2017-07-251-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep) takes the chip in and out of sleep mode, depending on the value of sleep, which is interpreted as a boolean. To clarify that 'int sleep' is a boolean and not a sleep delay, change the function interface to: static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable) Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sven Van Asbroeck <thesven73@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: Convert to using %pOF instead of full_nameRob Herring2017-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-pwm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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*-. \ Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', ↵Lee Jones2017-09-055-2/+259
|\ \ \ | |_|/ |/| | | | | 'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged
| | * mfd: twl: Move header file out of I2C realmWolfram Sang2017-09-042-2/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Jonathan Cameron <jic23@kernel.org> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
| * pwm: Add STM32 LPTimer PWM driverFabrice Gasnier2017-09-043-0/+257
|/ | | | | | | | | Add support for single PWM channel on Low-Power Timer, that can be found on some STM32 platforms. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* Merge tag 'pwm/for-4.13-rc1' of ↵Linus Torvalds2017-07-137-132/+211
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This release cycle's changes include mostly updates and cleanups to existing drivers along with a few cleanups to the core, documentation and device tree bindings" * tag 'pwm/for-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: cros-ec: Fix transposed param settings pwm: meson: Improve PWM calculation precision dt-bindings: pwm: meson: Add compatible for gxbb ao PWMs pwm: meson: Add compatible for the gxbb ao PWMs pwm: sun4i: Drop legacy callbacks pwm: sun4i: Switch to atomic PWM pwm: sun4i: Improve hardware read out pwm: hibvt: Constify hibvt_pwm_ops pwm: Silently error out on EPROBE_DEFER pwm: Standardize document format pwm: bfin: Remove unneeded error message dt-bindings: pwm: Update STM32 timers clock names dt-bindings: pwm: Add R-Car M3-W device tree bindings pwm: tegra: Set maximum pwm clock source per SoC tapeout
| * Merge branch 'for-4.13/drivers' into for-nextThierry Reding2017-07-066-131/+208
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| | * pwm: cros-ec: Fix transposed param settingsNick Vaccaro2017-07-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __cros_ec_pwm_get_duty() routine was transposing the insize and outsize fields when calling cros_ec_cmd_xfer_status(). The original code worked without error due to size of the two particular parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is not fixing an actual runtime problem, just correcting the calling usage. Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: meson: Improve PWM calculation precisionJerome Brunet2017-07-061-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using input clocks with high rates, such as clk81 (166MHz), the fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error. Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000 fin_ns = 5,9999999 which is, of course, rounded down to 5. This introduces an error of ~20% on the period requested from the PWM. This patch uses ps instead of ns (and 64 bit integers) to perform the calculation. This should give a good enough precision. Fixes: 211ed630753d ("pwm: Add support for Meson PWM Controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> squash! pwm: meson: Improve pwm calculation precision
| | * pwm: meson: Add compatible for the gxbb ao PWMsJerome Brunet2017-07-061-3/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the gxbb (and gxl) family, the PWMs of the AO domain require a specific compatible because the possible input clocks are different from the EE PWMs input clocks. Since the number of possible input clocks is also different, the 'num_parents' field is added to all the Meson PWM data. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Drop legacy callbacksAlexandre Belloni2017-07-061-160/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the legacy callbacks .enable(), .disable(), .set_polarity() and .config(). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Switch to atomic PWMAlexandre Belloni2017-07-061-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the driver to atomic PWM. This makes it easier to wait a proper amount of time when changing the duty cycle before disabling the channel (main use case is switching the duty cycle to 0 before disabling). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Improve hardware read outAlexandre Belloni2017-07-061-19/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement .get_state instead of only reading the polarity at probe time. This allows to get the proper state, period and duty cycle. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: hibvt: Constify hibvt_pwm_opsArvind Yadav2017-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | File size before: text data bss dec hex filename 1510 296 0 1806 70e drivers/pwm/pwm-hibvt.o File size After adding 'const': text data bss dec hex filename 1606 192 0 1798 706 drivers/pwm/pwm-hibvt.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: bfin: Remove unneeded error messageMarkus Elfring2017-07-061-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: tegra: Set maximum pwm clock source per SoC tapeoutLaxman Dewangan2017-06-131-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PWM hardware IP is taped-out with different maximum frequency on different SoCs. From HW team: Before Tegra186, it is 48 MHz. In Tegra186, it is 102 MHz. Add support to limit the clock source frequency to the maximum IP supported frequency. Provide these values via SoC chipdata. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * | pwm: Silently error out on EPROBE_DEFERJerome Brunet2017-07-061-1/+3
| |/ | | | | | | | | | | | | | | | | In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we shouldn't print an error message. Just be silent in this case. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* / pwm: jz4740: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-29/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. One inherent problem of this new approach is that the pinctrl framework does not allow us to configure each pin on demand, when the various PWM channels are requested or released. For instance, the PWM channels can be configured from sysfs, which would require all PWM pins to be configured properly beforehand for the PWM function, eventually causing conflicts with other platform or board drivers. The proper solution here would be to modify the pwm-jz4740 driver to handle only one PWM channel, and create an instance of this driver for each one of the 8 PWM channels. Then, it could use the pinctrl framework to dynamically configure the PWM pin it controls. Until this can be done, the only jz4740 board supported upstream (Qi lb60) can configure all of its connected PWM pins in PWM function mode, since those are not used by other drivers nor by GPIOs on the board. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'for-4.12/drivers' into for-nextThierry Reding2017-04-137-309/+605
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| * pwm: tegra: Read PWM clock source rate in driver initLaxman Dewangan2017-04-131-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is required to know the PWM clock source frequency to calculate the PWM period. In driver, the clock source frequency of the PWM does not get change and, hence, get the clock source frequency in driver init. Get this values later for period calculation from pwm_config(). This will help in avoiding the clock call for getting clock rate in the pwm_config() each time. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: pca9685: Fix GPIO-only operationSven Van Asbroeck2017-04-131-33/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO-only driver operation never clears the SLEEP bit, which can cause the GPIOs to become unusable. Example: 1. user requests first PWM -> driver clears SLEEP bit 2. user frees last PWM -> driver sets SLEEP bit 3. user requests GPIO 4. user switches GPIO on -> output does not turn on because SLEEP bit is set Prevent this behaviour by letting the runtime PM framework control the SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported or in use. Fixes: bccec89f0a35 ("Allow any of the 16 PWMs to be used as a GPIO") Reported-by: Sven Van Asbroeck <TheSven73@googlemail.com> Signed-off-by: Sven Van Asbroeck <TheSven73@googlemail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Don't explicitly set .ownerkbuild test robot2017-04-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: John Crispin <john@phrozen.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Avoid potential overflow for short periodsThierry Reding2017-04-131-6/+4
| | | | | | | | | | | | | | | | | | | | For very short periods, the result of the division might overflow the unsigned long hz variable (on 32-bit architectures). Avoid that by making it an unsigned long long. While at it, also remove an unneeded local variable whose only purpose is to store a temporary computation. Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Add support to configure pin state in suspends/resumeLaxman Dewangan2017-04-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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