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* reset: hisilicon: Use dev_err_probe instead of dev_errWang Ming2023-07-281-2/+2
| | | | | | | | | | The probe process may generate EPROBE_DEFER. In this case, dev_err_probe can still record err information. This helps simplify code and standardize error output. Signed-off-by: Wang Ming <machel@vivo.com> Link: https://lore.kernel.org/r/20230726114555.5011-1-machel@vivo.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* reset: reset-zynqmp: add support for Versal NET platformPiyush Mehta2023-07-281-0/+7
| | | | | | | | | | | Updated the reset driver to support Versal NET platform. As part of adding support for versal NET: - Added Versal NET specific compatible string. - Reset Id and number of resets. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230721041119.4058430-3-piyush.mehta@amd.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* reset: Explicitly include correct DT includesRob Herring2023-07-2815-14/+11
| | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20230714174939.4063667-1-robh@kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* Merge tag 'soc-drivers-6.5' of ↵Linus Torvalds2023-06-3014-166/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Nothing surprising in the SoC specific drivers, with the usual updates: - Added or improved SoC driver support for Tegra234, Exynos4121, RK3588, as well as multiple Mediatek and Qualcomm chips - SCMI firmware gains support for multiple SMC/HVC transport and version 3.2 of the protocol - Cleanups amd minor changes for the reset controller, memory controller, firmware and sram drivers - Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm, amlogic and renesas SoC specific drivers" * tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (118 commits) dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding MAINTAINERS: add PHY-related files to Amlogic SoC file list drivers: meson: secure-pwrc: always enable DMA domain tee: optee: Use kmemdup() to replace kmalloc + memcpy soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer dt-bindings: sram: qcom,imem: document qdu1000 soc: qcom: icc-bwmon: Fix MSM8998 count unit dt-bindings: soc: qcom,rpmh-rsc: Require power-domains soc: qcom: socinfo: Add Soc ID for IPQ5300 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300 soc: qcom: Fix a IS_ERR() vs NULL bug in probe soc: qcom: socinfo: Add support for new fields in revision 19 soc: qcom: socinfo: Add support for new fields in revision 18 dt-bindings: firmware: scm: Add compatible for SDX75 soc: qcom: mdt_loader: Fix split image detection dt-bindings: memory-controllers: drop unneeded quotes soc: rockchip: dtpm: use C99 array init syntax firmware: tegra: bpmp: Add support for DRAM MRQ GSCs soc/tegra: pmc: Use devm_clk_notifier_register() soc/tegra: pmc: Simplify debugfs initialization ...
| * reset: mpfs: select AUXILIARY_BUSPhilipp Zabel2023-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Cc: Daire McNamara <daire.mcnamara@microchip.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230502102041.1418397-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: starfive: select AUXILIARY_BUSPhilipp Zabel2023-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20230502102050.1418417-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: oxnas: remove obsolete reset driverNeil Armstrong2023-05-083-118/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 peripheral reset. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230331-topic-oxnas-upstream-remove-v1-17-5bd58fd1dd1f@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: sti: simplify driver's config and buildLukas Bulwahn2023-05-082-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 64933513e461 ("reset: sti: Remove STiH415/6 reset support"), there is only one sti reset driver left and there no need to define a dedicated config STI_RESET_SYSCFG, which is selected by the config for the STiH407 reset driver. Simply add reset-syscfg.c to the build for the STiH407 reset driver. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20230330112347.31137-2-lukas.bulwahn@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: meson-audio-arb: Use dev_err_probe()Ye Xingchen2023-05-081-5/+2
| | | | | | | | | | | | | | | | | | Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/202303231653447704556@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: sti: rely on regmap_field_read_poll_timeout for ack waitAlain Volmat2023-05-081-14/+4
| | | | | | | | | | | | | | | | | | | | Use regmap_field_read_poll_timeout function when waiting for the ack bit upon performing the reset control. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20230210224332.98482-1-avolmat@me.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: brcmstb-rescal: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/202302161052126378140@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: meson: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/202302161054598138273@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: reset-hsdk: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-5/+2
| | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202302161056304138337@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: lpc18xx: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202302161053360618204@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: axs10x: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202302161050336958071@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: ath79: Use devm_platform_ioremap_resource()Ye Xingchen2023-05-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202302161049100728015@zte.com.cn Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* | reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35Geert Uytterhoeven2023-06-061-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nuvoton MA35D1 reset controller is only present on Nuvoton MA35 SoCs. Hence add a dependency on ARCH_MA35, to prevent asking the user about this driver when configuring a kernel without MA35 SoC support. Also, do not enable the driver by default when merely compile-testing. While at it, fix a misspelling of "Nuvoton". Fixes: e4bb55d6ccf0f774 ("reset: Add Nuvoton ma35d1 reset driver support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | reset: Add Nuvoton ma35d1 reset driver supportJacky Huang2023-06-053-0/+242
|/ | | | | | | | | | This driver supports individual IP reset for the MA35D1. The reset control registers are a subset of the system control registers. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-04-309-181/+319
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Nothing looks out of the ordinary in this batch of clk driver updates. There are a couple patches to the core clk framework, but they're all basically cleanups or debugging aids. The driver updates and new additions are dominated in the diffstat by Qualcomm and MediaTek drivers. Qualcomm gained a handful of new drivers for various SoCs, and MediaTek gained a bunch of drivers for MT8188. The MediaTek drivers are being modernized as well, so there are updates all over that vendor's clk drivers. There's also a couple other new clk drivers in here, for example the Starfive JH7110 SoC support is added. Outside of the two major SoC vendors though, we have the usual collection of non-critical fixes and cleanups to various clk drivers. It's good to see that we're getting more cleanups and modernization patches. Maybe one day we'll be able to properly split clk providers from clk consumers. Core: - Print an informational message before disabling unused clks New Drivers: - BCM63268 timer clock and reset controller - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Clk driver support for Loongson-2 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators - Initial Starfive JH7110 clk/reset support - Global clock controller drivers for Qualcomm SM7150, IPQ9574, MSM8917 and IPQ5332 SoCs - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P SoCs Updates: - Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() - Convert platform clk drivers to remove_new() - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Reimplement Loongson-1 clk driver with DT support - Migrate socfpga clk driver to of_clk_add_hw_provider() - Support for i3c clks on Aspeed ast2600 SoCs - Add clock generic devm_clk_hw_register_gate_parent_data - Add audiomix block control for i.MX8MP - Add support for determine_rate to i.MX composite-8m - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate - Provide clock name in error message for clk-gpr-mux on get parent failure - Drop duplicate imx_clk_mux_flags macro - Register the i.MX8MP Media Disp2 Pix clock as bus clock - Add Media LDB root clock to i.MX8MP - Make i.MX8MP nand_usdhc_bus clock as non-critical - Fix the rate table for i.MX fracn-gppll - Disable HW control for the fracn-gppll in order to be controlled by register write - Add support for interger PLL in fracn-gppll - Add mcore_booted module parameter to i.MX93 provider - Add NIC, A55 and ARM PLL clocks to i.MX93 - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical - Update some of the i.MX critical clocks flags to allow glitchless on-the-fly rate change. - Add I2C5 clock on Renesas R-Car V3H - Exynos850: Add CMU_G3D clock controller for the Mali GPU - Extract Exynos5433 (ARM64) clock controller power management code to common driver parts - Exynos850: make PMU_ALIVE_PCLK clock critical - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car V4H - Add video capture (VIN) clocks on Renesas R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H - Support for Stromer Plus PLL on Qualcomm IPQ5332 - Add a missing reset to Qualcomm QCM2290 - Migrate Qualcomm IPQ4019 to clk_parent_data - Make USB GDSCs enter retention state when disabled on Qualcomm SM6375, MSM8996 and MSM8998 SoCs - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk - Add two EMAC GDSCs on Qualcomm SC8280XP - Use shared rcg clk ops in Qualcomm SM6115 GCC - Park Qualcomm SM8350 PCIe PIPE clks when disabled - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller - Add missing XO clocks to Qualcomm MSM8226 and MSM8974 - Convert some Qualcomm clk DT bindings to YAML - Reparenting fix for the clock supplying camera modules on Rockchip rk3399 - Mark more critical (bus-)clocks on Rockchip rk3588" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: rockchip: rk3588: make gate linked clocks critical clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: starfive: Avoid casting iomem pointers clk: microchip: fix potential UAF in auxdev release callback clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: mediatek: fhctl: Mark local variables static clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` ...
| * clk: starfive: Avoid casting iomem pointersStephen Boyd2023-04-141-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip up tools like sparse, and make for some awkward casts that are largely unnecessary. While we're here, change the allocation from devm and actually free the auxiliary_device memory in the release function. This avoids any use after free problems where the parent device driver is unbound from the device but the auxiliuary_device is still in use accessing devm freed memory. Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: Hal Feng <hal.feng@starfivetech.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230413205528.4044216-1-sboyd@kernel.org
| * reset: starfive: Add StarFive JH7110 reset driverHal Feng2023-04-053-0/+79
| | | | | | | | | | | | | | | | | | | | Add auxiliary driver to support StarFive JH7110 system and always-on resets. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: starfive: jh71x0: Use 32bit I/O on 32bit registersEmil Renner Berthing2023-04-053-24/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: starfive: Rename "jh7100" to "jh71x0" for the common codeEmil Renner Berthing2023-04-053-27/+27
| | | | | | | | | | | | | | | | | | | | | | For the common code will be shared with the StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: starfive: Extract the common JH71X0 reset codeEmil Renner Berthing2023-04-053-54/+76
| | | | | | | | | | | | | | | | | | | | | | | | Extract the common JH71X0 reset code for reusing them to support JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: starfive: Factor out common JH71X0 reset codeEmil Renner Berthing2023-04-055-149/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the reset registers don't get their own memory range, but instead follow the clock control registers. The registers still follow the same structure though, so let's factor out the common code to handle all these cases. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: Create subdirectory for StarFive driversEmil Renner Berthing2023-04-055-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng2023-04-051-2/+2
| | | | | | | | | | | | | | | | | | | | Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* | reset: mpfs: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Daire McNamara <daire.mcnamara@microchip.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-riscv@lists.infradead.org Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
* | reset: lantiq: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
* | reset: mchp: sparx5: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-131-1/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Lars Povlsen <lars.povlsen@microchip.com> Cc: Steen Hegelund <Steen.Hegelund@microchip.com> Cc: Daniel Machon <daniel.machon@microchip.com> Cc: UNGLinuxDriver@microchip.com Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
* reset: uniphier-glue: Fix possible null-ptr-derefHui Tang2023-01-031-3/+1
| | | | | | | | | | | It will cause null-ptr-deref when resource_size(res) invoked, if platform_get_resource() returns NULL. Fixes: 499fef09a323 ("reset: uniphier: add USB3 core reset control") Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221114004958.258513-1-tanghui20@huawei.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* reset: ti-sci: honor TI_SCI_PROTOCOL setting when not COMPILE_TESTRandy Dunlap2023-01-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is a build error when COMPILE_TEST=y, TI_SCI_PROTOCOL=m, and RESET_TI_SCI=y: drivers/reset/reset-ti-sci.o: in function `ti_sci_reset_probe': reset-ti-sci.c:(.text+0x22c): undefined reference to `devm_ti_sci_get_handle' Fix this by making RESET_TI_SCI honor the Kconfig setting of TI_SCI_PROTOCOL when COMPILE_TEST is not set. When COMPILE_TEST is set, TI_SCI_PROTOCOL must be disabled (=n). Fixes: a6af504184c9 ("reset: ti-sci: Allow building under COMPILE_TEST") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <kristo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221030055636.3139-1-rdunlap@infradead.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2022-10-083-1/+165
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
| * reset: add polarfire soc reset supportConor Dooley2022-09-143-1/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
* | Merge tag 'arm-drivers-6.1' of ↵Linus Torvalds2022-10-061-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "The drivers branch for 6.1 is a bit larger than for most releases. Most of the changes come from SoC maintainers for the drivers/soc subsystem: - A new driver for error handling on the NVIDIA Tegra 'control backbone' bus. - A new driver for Qualcomm LLCC/DDR bandwidth measurement - New Rockchip rv1126 and rk3588 power domain drivers - DT binding updates for memory controllers, older Rockchip SoCs, various Mediatek devices, Qualcomm SCM firmware - Minor updates to Hisilicon LPC bus, the Allwinner SRAM driver, the Apple rtkit firmware driver, Tegra firmware - Minor updates for SoC drivers (Samsung, Mediatek, Renesas, Tegra, Qualcomm, Broadcom, NXP, ...) There are also some separate subsystem with downstream maintainers that merge updates this way: - Various updates and new drivers in the memory controller subsystem for Mediatek and Broadcom SoCs - Small set of changes in preparation to add support for FF-A v1.1 specification later, in the Arm FF-A firmware subsystem - debugfs support in the PSCI firmware subsystem" * tag 'arm-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (149 commits) ARM: remove check for CONFIG_DEBUG_LL_SER3 firmware/psci: Add debugfs support to ease debugging firmware/psci: Print a warning if PSCI doesn't accept PC mode dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support soc: sunxi: sram: Add support for the D1 system control soc: sunxi: sram: Export the LDO control register soc: sunxi: sram: Save a pointer to the OF match data soc: sunxi: sram: Return void from the release function soc: apple: rtkit: Add apple_rtkit_poll soc: imx: add i.MX93 media blk ctrl driver soc: imx: add i.MX93 SRC power domain driver soc: imx: imx8m-blk-ctrl: Use genpd_xlate_onecell soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR soc: imx: add icc paths for i.MX8MP hsio/hdmi blk ctrl soc: imx: add icc paths for i.MX8MP media blk ctrl ...
| * | arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCAWilliam Zhang2022-08-151-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Guenter Roeck <linux@roeck-us.net> (for watchdog) Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci) Acked-by: Wolfram Sang <wsa@kernel.org> (for i2c) Acked-by: Philipp Zabel <p.zabel@pengutronix.de> (for reset) Link: https://lore.kernel.org/r/20220803175455.47638-7-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | reset: npcm: fix iprst2 and iprst4 settingTomer Maimon2022-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In NPCM8XX USB reset sequence, iprst2 register was set with iprst4 value and iprst4 register wasn´t set. This fix sets the correct IP reset values in iprst2 and iprst4 registers in NPCM8XX USB reset sequence. Fixes: fc5d2a2f4aa5 ("reset: npcm: Add NPCM8XX support") Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220922153856.23326-1-tmaimon77@gmail.com
* | reset: microchip-sparx5: issue a reset on startupMichael Walle2022-08-301-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally this was used in by the switch core driver to issue a reset. But it turns out, this isn't just a switch core reset but instead it will reset almost the complete SoC. Instead of adding almost all devices of the SoC a shared reset line, issue the reset once early on startup. Keep the reset controller for backwards compatibility, but make the actual reset a noop. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Steen Hegelund <Steen.Hegelund@microchip.com> on Sparx5 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220826115607.1148489-2-michael@walle.cc
* | reset: imx7: Fix the iMX8MP PCIe PHY PERST supportRichard Zhu2022-08-301-0/+1
|/ | | | | | | | | | | | | | | | | | On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here. Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1661845564-11373-5-git-send-email-hongxing.zhu@nxp.com
* Merge tag 'arm-late-6.0' of ↵Linus Torvalds2022-08-053-2/+138
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These updates came in after I had already tagged the branches, but they still seem appropriate for 6.0 and most of them were part of linux-next through other trees. - The reset controller tree adds one new driver for the TI TPS380x power management chip and a few minor changes in other drivers - Apple M1 now has a DT entry for the NVMe controller after the driver was merged, and has a new mailing list in the MAINTAINERS file. - Fixes for USB on the Socionext Uniphier platforms and the network controller on Intel Cyclone5" * tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: uniphier: Fix USB interrupts for PXs3 SoC ARM: dts: uniphier: Fix USB interrupts for PXs2 SoC arm64: dts: apple: t8103: Add ANS2 NVMe nodes reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" reset: tps380x: Add TPS380x device driver supprt dt-bindings: reset: Add TPS380x documentation dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G2UL USBPHY Control bindings ARM: dts: add EMAC AXI settings for Cyclone5 reset: reset-simple should depends on HAS_IOMEM Revert "reset: microchip-sparx5: allow building as a module" reset: a10sr: allow building under COMPILE_TEST reset: allow building of reset simple driver if expert config selected reset: microchip-sparx5: allow building as a module arm64: dts: apple: Re-parent ANS2 power domains MAINTAINERS: add ARM/APPLE MACHINE mailing list
| * reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage"Colin Ian King2022-07-281-1/+1
| | | | | | | | | | | | | | | | There is a spelling mistake in the MODULE_DESCRIPTION text. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220728110554.18320-1-colin.i.king@gmail.com
| * reset: tps380x: Add TPS380x device driver supprtMarco Felsch2022-07-273-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI TPS380x family [1] is a voltage supervisor with a dedicated manual reset (mr) line input and a reset output. The chip(s) have a build in reset delay, depending on the chip partnumber. This simple driver addresses this so the cosumer don't need to care about it. [1] https://www.ti.com/product/TPS3801 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> [p.zabel@pengutronix.de: drop Todo comment about min/typ/max reset time] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220530092226.748644-2-m.felsch@pengutronix.de
| * reset: reset-simple should depends on HAS_IOMEMBen Dooks2022-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset-simple driver does not build on all architecuters as it requires devm_ioremap_resource() which is only built when CONFIG_HAS_IOMEM is enabled in the kenrel. Fix the following error by depending on CONFIG_HAS_IOMEM: drivers/reset/reset-simple.o: in function `reset_simple_probe': reset-simple.c:(.text+0x3aa): undefined reference to `devm_ioremap_resource' Fixes: 18d1909be345 ("reset: allow building of reset simple driver if expert config selected") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220719085200.203688-1-ben.dooks@sifive.com
| * Revert "reset: microchip-sparx5: allow building as a module"Philipp Zabel2022-07-132-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b6b9585876da018bdde2d5f15d206a689c0d70f3. This breaks MDIO on kswitch-d10, presumably because the global switch reset is not released early enough anymore. Reported-by: Michael Walle <michael@walle.cc> Cc: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220713084010.168720-1-p.zabel@pengutronix.de
| * reset: a10sr: allow building under COMPILE_TESTPhilipp Zabel2022-07-111-1/+1
| | | | | | | | | | | | | | This driver can be built under COMPILE_TEST. Allow it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220711130624.1217599-1-p.zabel@pengutronix.de
| * reset: allow building of reset simple driver if expert config selectedBen Dooks2022-07-111-1/+1
| | | | | | | | | | | | | | | | | | If CONFIG_EXPERT is selected, allow selection of CONFIG_RESET_SIMPLE if needed by the user. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220708165656.269507-1-ben.dooks@sifive.com
| * reset: microchip-sparx5: allow building as a moduleClément Léger2022-06-292-7/+3
| | | | | | | | | | | | | | | | | | Set RESET_MCHP_SPARX5 as a tristate and add MODULE_DEVICE_TABLE() to allow building this driver as a module. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220617103730.490588-1-clement.leger@bootlin.com
* | Merge tag 'spdx-6.0-rc1' of ↵Linus Torvalds2022-08-042-18/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx Pull SPDX updates from Greg KH: "Here is the set of SPDX comment updates for 6.0-rc1. Nothing huge here, just a number of updated SPDX license tags and cleanups based on the review of a number of common patterns in GPLv2 boilerplate text. Also included in here are a few other minor updates, two USB files, and one Documentation file update to get the SPDX lines correct. All of these have been in the linux-next tree for a very long time" * tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits) Documentation: samsung-s3c24xx: Add blank line after SPDX directive x86/crypto: Remove stray comment terminator treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE ...
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULEThomas Gleixner2022-06-102-18/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | Merge branch 'nuvoton/newsoc' into arm/newsocArnd Bergmann2022-07-191-34/+173
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge the new SoC support from Tomer Maimon: "This patchset adds initial support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family. The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. The NPCM8XX computing subsystem comprises a quadcore ARM Cortex A35 ARM-V8 architecture. This patchset adds minimal architecture and drivers such as: Clocksource, Clock, Reset, and WD. Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. This patchset was tested on the Arbel NPCM8XX evaluation board." I'm leaving out the clk controller driver, which is still under review. * nuvoton/newsoc: arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 10:17:13 +0100