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* sched/headers: Prepare to move signal wakeup & sigpending methods from ↵Ingo Molnar2017-03-021-1/+1
| | | | | | | | | | | | | <linux/sched.h> into <linux/sched/signal.h> Fix up affected files that include this signal functionality via sched.h. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
* Merge tag 'rtc-4.11' of ↵Linus Torvalds2017-02-2822-252/+1855
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC updates from Alexandre Belloni: "Subsystem: - constify rtc_class_ops structures New driver: - STM32 Drivers: - armada38x: fix errata, Armada 7K/8K support - ds3232: fix wakeup support - gemini: DT support - m48t86: huge cleanup and platform_data removal - mcp795: alarm support - sun6i: proper oscillator handling - tegra: proper clock handling - tps65910: calibration support" * tag 'rtc-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (44 commits) rtc: ds3232: Call device_init_wakeup before device_register rtc: pcf2127: bulk read only date and time registers. rtc: armada38x: Add support for Armada 7K/8K rtc: armada38x: Prepare driver to manage different versions rtc: ds3232: Add regmap max_register definition. rtc: ds3232: Cleanup whitespace around register and bit definitions. rtc: m48t86: remove unused platform_data ARM: Orion5x: ts78xx: allow rtc-m48t86 to manage it's own resources ARM: Orion5x: ts78xx: remove RTC detection ARM: ep93xx: ts72xx: allow rtc-m48t86 to manage its own resources rtc: m48t86: verify that the RTC is actually present rtc: m48t86: add NVRAM support rtc: m48t86: allow driver to manage its resources rtc: m48t86: shorten register name defines bindings: rtc: correct wrong reference in required properties rtc: sun6i: Fix return value check in sun6i_rtc_clk_init() rtc: sun6i: extend test coverage rtc: sun6i: Fix compatibility with old DT binding rtc: snvs: add a missing write sync rtc: bq32000: add support to enable disable the trickle charge FET bypass ...
| * rtc: ds3232: Call device_init_wakeup before device_registerPhil Reid2017-02-241-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wakealarm attribute is currently not exposed in the sysfs interface as the device has not been set as doing wakealarm when device_register is called. Changing the order of the calls fixes that problem. Interrupts are cleared in check_rtc_status prior to requesting the interrupt. This is only set if an irq is defined. If irq registration fails then set wakeup_capable to false. With this change the sysfs wakealarm attribute will be left visible but it is non functional. rtcwake still returns that the device is not enabled for wakeup. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: pcf2127: bulk read only date and time registers.Sean Nyekjaer2017-02-231-2/+13
| | | | | | | | | | | | | | | | Read control registers one by one and bulk read time registers. This fixes when the clock is read, the watchdog counter register is zeroed. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: armada38x: Add support for Armada 7K/8KGregory CLEMENT2017-02-211-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 7K/8K use the same RTC IP than the Armada 38x. However the SOC integration differs in 2 points: - MBUS bridge timing initialization - IRQ configuration at SoC level Moreover the Armada 7K/8K have an issue preventing to get the interrupt from alarm 1. This commit allows to use alarm 2 for these A7K/8K but to still use alarm 1 for the Armada 38x. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: armada38x: Prepare driver to manage different versionsGregory CLEMENT2017-02-211-53/+99
| | | | | | | | | | | | | | | | | | | | | | | | In order to prepare the introduction of the A7K/A8K version of the RTC, this commit introduces a new data structure. This structure allows to handle the differences between the integration of the RTC IP in the SoCs. It will be: - MBUS bridge timing initialization - IRQ configuration at SoC level Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: ds3232: Add regmap max_register definition.Phil Reid2017-02-211-0/+2
| | | | | | | | | | | | | | | | Add the max_register to the regmap_config definition. This allows dumping of the device's registers via the regmap debugfs interface. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: ds3232: Cleanup whitespace around register and bit definitions.Phil Reid2017-02-211-22/+22
| | | | | | | | | | | | | | | | Whitespace was a combination of spaces and tabs. Use spaces and align register / bit definitions. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: m48t86: remove unused platform_dataH Hartley Sweeten2017-02-211-32/+19
| | | | | | | | | | | | | | | | | | | | | | All users of this driver have been updated to allow the driver to manage it's own resources and do the read/write operations internally. The m48t86_ops are no longer used. Remove the platform_data header and the support code in the driver. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: m48t86: verify that the RTC is actually presentH Hartley Sweeten2017-02-211-0/+36
| | | | | | | | | | | | | | | | | | The RTC is an optional feature at purchase time on some Technologic Systems boards. Verify that it actually exists by checking if the last two bytes of the NVRAM can be changed. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: m48t86: add NVRAM supportH Hartley Sweeten2017-02-121-0/+41
| | | | | | | | | | | | | | | | This RTC has 114 bytes of NVRAM. Provide access to it via a binary sysfs 'nvram' attribute file. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: m48t86: allow driver to manage its resourcesH Hartley Sweeten2017-02-121-51/+102
| | | | | | | | | | | | | | | | Allow this driver to, optionally, manage it's own resources and do the read/write operations if the platform does not provide them. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: m48t86: shorten register name definesH Hartley Sweeten2017-02-121-64/+63
| | | | | | | | | | | | | | | | | | For aesthetics. Shorten all the register names by removing '_REG' from all of them. This helps fix all the checkpatch.pl issues. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Fix return value check in sun6i_rtc_clk_init()Wei Yongjun2017-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | In case of error, the function of_io_request_and_map() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: extend test coverageAlexandre Belloni2017-02-011-2/+3
| | | | | | | | | | | | | | | | COMPILE_TEST was wrongly placed, move it to the "depends on" line. Also depend on COMMON_CLK as the driver now needs it to be properly compiled. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Fix compatibility with old DT bindingChen-Yu Tsai2017-02-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator") adds a new clock for the rtc block with a 2 step probe mechanism. To share the register region between both the clock and rtc instance, a static pointer is used to keep the related data structure. To preserve compatibility with the old binding, the data structure should be saved as soon as the registers are mapped in, regardless of the presence of the clock bindings, so that the rtc device can retrieve it when it is probed. This fixes the rtc device not probing when we use the updated driver with an old device tree blob. Fixes: 847b8bf62eb4 ("rtc: sun6i: Expose the 32kHz oscillator") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: snvs: add a missing write syncGuy Shapiro2017-02-011-0/+1
| | | | | | | | | | | | | | | | | | The clear of the LPTA_EN flag should be synced before writing to the alarm register. Omitting this synchronization creates a race when trying to change existing alarm. Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: bq32000: add support to enable disable the trickle charge FET bypassEnric Balletbo i Serra2017-02-011-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bq32000 includes a trickle charge circuit to maintain the charge of the backup supply when a super capacitor is used. You can enable the charging circuit by setting 'trickle-resistor-ohms', additionally you can set TCFE to 1 to bypass the internal diode and boost the charge voltage of the backup supply. You might want to enable/disable the TCFE switch from userspace (e.g when device is only connected to a battery) This patch introduces a new sysfs entry to enable and disable this FET form userspace. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Switch to devm_rtc_device_registerMaxime Ripard2017-02-011-12/+2
| | | | | | | | | | | | | | Now that we have a devm variant of rtc_device_register, switch to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Expose the 32kHz oscillatorMaxime Ripard2017-02-011-13/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC controls the input source of the main 32kHz oscillator in the system, feeding it to the clock unit too. By default, this is using an internal, very inaccurate (+/- 30%) oscillator with a divider to make it roughly around 32kHz. This is however quite impractical for the RTC, since our time will not be tracked properly. Since this oscillator is an input of the main clock unit, and since that clock unit will be probed using CLK_OF_DECLARE, we have to use it as well, leading to a two stage probe: one to enable the clock, the other one to enable the RTC. There is also a slight change in the binding that is required (and should have been from the beginning), since we'll need a phandle to the external oscillator used on that board. We support the old binding by not allowing to switch to the external oscillator and only using the internal one (which was the previous behaviour) in the case where we're missing that phandle. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Switch to the external oscillatorMaxime Ripard2017-02-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC is clocked from either an internal, imprecise, oscillator or an external one, which is usually much more accurate. The difference perceived between the time elapsed and the time reported by the RTC is in a 10% scale, which prevents the RTC from being useful at all. Fortunately, the external oscillator is reported to be mandatory in the Allwinner datasheet, so we can just switch to it. Cc: stable@vger.kernel.org Fixes: 9765d2d94309 ("rtc: sun6i: Add sun6i RTC driver") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Add some lockingMaxime Ripard2017-02-011-2/+15
| | | | | | | | | | | | | | | | | | | | | | Some registers have a read-modify-write access pattern that are not atomic. Add some locking to prevent from concurrent accesses. Cc: stable@vger.kernel.org Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: sun6i: Disable the build as a moduleMaxime Ripard2017-01-242-7/+2
| | | | | | | | | | | | | | | | | | Since we have to provide the clock very early on, the RTC driver cannot be built as a module. Make sure that won't happen. Cc: stable@vger.kernel.org Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: gemini: Add device tree probingLinus Walleij2017-01-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds bindings and simple probing for the Cortina Systems Gemini SoC RTC. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: stm32: fix comparison warningsAmelie Delaunay2017-01-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches fixes comparison between signed and unsigned values as it could produce an incorrect result when the signed value is converted to unsigned: drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_valid_alrm': drivers/rtc/rtc-stm32.c:404:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] if ((((tm->tm_year > cur_year) && ... It also fixes comparison always true or false due to the fact that unsigned value is compared against zero with >= or <: drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_init': drivers/rtc/rtc-stm32.c:514:35: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] for (pred_a = pred_a_max; pred_a >= 0; pred_a-- ) { drivers/rtc/rtc-stm32.c:530:44: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] (rate - ((pred_a + 1) * (pred_s + 1)) < 0) ? Fixes: 4e64350f42e2 ("rtc: add STM32 RTC driver") Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: stm32: use 0 instead of ~PWR_CR_DBP in regmap_update_bitsAmelie Delaunay2017-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the ~ operator on a BIT() constant results in a large 'unsigned long' constant that won't fit into an 'unsigned int' function argument on 64-bit architectures, resulting in a harmless build warning in x86 allmodconfig: drivers/rtc/rtc-stm32.c: In function 'stm32_rtc_probe': drivers/rtc/rtc-stm32.c:651:51: error: large integer implicitly truncated to unsigned type [-Werror=overflow] regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, ~PWR_CR_DBP); As PWR_CR_DBP mask prevents other bits to be cleared, replace all ~PWR_CR_DBP by 0. Fixes: 4e64350f42e2 ("rtc: add STM32 RTC driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: tegra: Implement clock handlingThierry Reding2017-01-231-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing the registers of the RTC block on Tegra requires the module clock to be enabled. This only works because the RTC module clock will be enabled by default during early boot. However, because the clock is unused, the CCF will disable it at late_init time. This causes the RTC to become unusable afterwards. This can easily be reproduced by trying to use the RTC: $ hwclock --rtc /dev/rtc1 This will hang the system. I ran into this by following up on a report by Martin Michlmayr that reboot wasn't working on Tegra210 systems. It turns out that the rtc-tegra driver's ->shutdown() implementation will hang the CPU, because of the disabled clock, before the system can be rebooted. What confused me for a while is that the same driver is used on prior Tegra generations where the hang can not be observed. However, as Peter De Schrijver pointed out, this is because on 32-bit Tegra chips the RTC clock is enabled by the tegra20_timer.c clocksource driver, which uses the RTC to provide a persistent clock. This code is never enabled on 64-bit Tegra because the persistent clock infrastructure does not exist on 64-bit ARM. The proper fix for this is to add proper clock handling to the RTC driver in order to ensure that the clock is enabled when the driver requires it. All device trees contain the clock already, therefore no additional changes are required. Reported-by: Martin Michlmayr <tbm@cyrius.com> Acked-By Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: tegra: Sort includes alphabeticallyThierry Reding2017-01-131-6/+7
| | | | | | | | | | | | | | | | | | The ordering of includes is currently completely arbitrary, making it impossible to decide where to put new includes. Remove the dilemma by sort the include list alphabetically. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: stm32: fix building without CONFIG_OFArnd Bergmann2017-01-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | The new driver has a stray #ifdef in it that causes a build error: drivers/rtc/rtc-stm32.c:718:21: error: 'stm32_rtc_of_match' undeclared here (not in a function); did you mean 'stm32_rtc_pm_ops'? As the #ifdef serves no purpose here, let's just remove it. Fixes: 4e64350f42e2 ("rtc: add STM32 RTC driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: stm32: remove __exit annotation on remove callbackArnd Bergmann2017-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The remove function can be called at runtime for a manual 'unbind' operation and must not be left out from a built-in driver, as kbuild complains: `stm32_rtc_remove' referenced in section `.data.stm32_rtc_driver' of drivers/rtc/rtc-stm32.o: defined in discarded section `.exit.text' of drivers/rtc/rtc-stm32.o This removes the extraneous annotation. Fixes: 4e64350f42e2 ("rtc: add STM32 RTC driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: add STM32 RTC driverAmelie Delaunay2017-01-133-0/+739
| | | | | | | | | | | | | | | | This patch adds support for the STM32 RTC. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: armada38x: make struct rtc_class_ops constRussell King2017-01-121-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada38x wants to modify its rtc_class_ops to remove the interrupt handling when there is no usable interrupt, but this means we leave function pointers in writable memory. Since rtc_class_ops is small, arrange to have two instances, one for when we have interrupts, and one for when we have none, both marked const. This allows the compiler to place them in read-only memory, which is better than placing them in __ro_after_init. Thanks to Bhumika Goyal <bhumirks@gmail.com> for pointing out that the structure was writable and submitting a patch to add __ro_after_init. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: constify rtc_class_ops structuresBhumika Goyal2017-01-117-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declare rtc_class_ops structures as const as they are only passed as an argument to the function devm_rtc_device_register. This argument is of type const struct rtc_class_ops *, so rtc_class_ops structures having this property can be declared const. Done using Coccinelle: @r1 disable optional_qualifier @ identifier i; position p; @@ static struct rtc_class_ops i@p = {...}; @ok1@ identifier r1.i; position p; @@ devm_rtc_device_register(...,&i@p,...) @bad@ position p!={r1.p,ok1.p}; identifier r1.i; @@ i@p @depends on !bad disable optional_qualifier@ identifier r1.i; @@ +const struct rtc_class_ops i; Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: imxdi: use the security violation interruptMartin Kaiser2017-01-111-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DryIce chipset has a dedicated security violation interrupt that is triggered for security violations (if configured to do so). According to the publicly available imx258 reference manual, irq 56 is used for this interrupt. If an irq number is provided for the security violation interrupt, install the same handler that we're already using for the "normal" interrupt. imxdi->irq is used only in the probe function, make it a local variable. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: mcp795: add alarm support.Emil Bartczak2017-01-111-1/+170
| | | | | | | | | | | | | | | | | | | | This patch adds alarm support. This allows to configure the chip to generate an interrupt when the alarm matches current time value. Alarm can be programmed up to one year in the future and is accurate to the second. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: mcp795: Add support for weekday.Emil Bartczak2017-01-111-5/+7
| | | | | | | | | | | | | | This patch adds support for saving/loading weekday value from the chip. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: armada38x: Follow the new recommendation for errata implementationGregory CLEMENT2017-01-111-23/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to RES-3124064: The device supports CPU write and read access to the RTC time register. However, due to this restriction, read and write from/to internal RTC register may fail. Workaround: General setup: 1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0) to value 0xFD4D4FFF Write RTC WRCLK Period to its maximum value (0x3FF) Write RTC WRCLK setup to 0x29 Write RTC WRCLK High Time to 0x53 (default value) Write RTC Read Output Delay to its maximum value (0x1F) Mbus - Read All Byte Enable to 0x1 (default value) 2. Configure the RTC Test Configuration Register (offset 0xA381C) bit3 to '1' (Reserved, Marvell internal) For any RTC register read operation: 1. Read the requested register 100 times. 2. Find the result that appears most frequently and use this result as the correct value. For any RTC register write operation: 1. Issue two dummy writes of 0x0 to the RTC Status register (offset 0xA3800). 2. Write the time to the RTC Time register (offset 0xA380C). This patch is based on the work of Shaker Daibes Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: tps65910: use 'unsigned int' instead of 'unsigned' in argumentsVesa Jääskeläinen2017-01-101-1/+2
| | | | | | | | | | | | | | | | Fixes checkpatch.pl warning: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: tps65910: Add RTC calibration supportVesa Jääskeläinen2017-01-101-0/+143
| | | | | | | | | | | | | | | | | | | | Texas Instrument's TPS65910 has support for compensating RTC crystal inaccuracies. When enabled every hour RTC counter value will be compensated with two's complement value. Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: rx8010: change lock mechanismFabien Lahoudere2017-01-041-21/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove spinlock and use the "rtc->ops_lock" from RTC subsystem instead. spin_lock_irqsave() is not needed here because we do not have hard IRQs. This patch fixes the following issue: root@GE004097290448 b850v3:~# hwclock --systohc root@GE004097290448 b850v3:~# hwclock --systohc root@GE004097290448 b850v3:~# hwclock --systohc root@GE004097290448 b850v3:~# hwclock --systohc root@GE004097290448 b850v3:~# hwclock --systohc [ 82.108175] BUG: spinlock wrong CPU on CPU#0, hwclock/855 [ 82.113660] lock: 0xedb4899c, .magic: dead4ead, .owner: hwclock/855, .owner_cpu: 1 [ 82.121329] CPU: 0 PID: 855 Comm: hwclock Not tainted 4.8.0-00042-g09d5410-dirty #20 [ 82.129078] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 82.135609] Backtrace: [ 82.138090] [<8010d378>] (dump_backtrace) from [<8010d5c0>] (show_stack+0x20/0x24) [ 82.145664] r7:ec936000 r6:600a0013 r5:00000000 r4:81031680 [ 82.151402] [<8010d5a0>] (show_stack) from [<80401518>] (dump_stack+0xb4/0xe8) [ 82.158636] [<80401464>] (dump_stack) from [<8017b8b0>] (spin_dump+0x84/0xcc) [ 82.165775] r10:00000000 r9:ec936000 r8:81056090 r7:600a0013 r6:edb4899c r5:edb4899c [ 82.173691] r4:e5033e00 r3:00000000 [ 82.177308] [<8017b82c>] (spin_dump) from [<8017bcb0>] (do_raw_spin_unlock+0x108/0x130) [ 82.185314] r5:edb4899c r4:edb4899c [ 82.188938] [<8017bba8>] (do_raw_spin_unlock) from [<8094b93c>] (_raw_spin_unlock_irqrestore+0x34/0x54) [ 82.198333] r5:edb4899c r4:600a0013 [ 82.201953] [<8094b908>] (_raw_spin_unlock_irqrestore) from [<8065b090>] (rx8010_set_time+0x14c/0x188) [ 82.211261] r5:00000020 r4:edb48990 [ 82.214882] [<8065af44>] (rx8010_set_time) from [<80653fe4>] (rtc_set_time+0x70/0x104) [ 82.222801] r7:00000051 r6:edb39da0 r5:edb39c00 r4:ec937e8c [ 82.228535] [<80653f74>] (rtc_set_time) from [<80655774>] (rtc_dev_ioctl+0x3c4/0x674) [ 82.236368] r7:00000051 r6:7ecf1b74 r5:00000000 r4:edb39c00 [ 82.242106] [<806553b0>] (rtc_dev_ioctl) from [<80284034>] (do_vfs_ioctl+0xa4/0xa6c) [ 82.249851] r8:00000003 r7:80284a40 r6:ed1e9c80 r5:edb44e60 r4:7ecf1b74 [ 82.256642] [<80283f90>] (do_vfs_ioctl) from [<80284a40>] (SyS_ioctl+0x44/0x6c) [ 82.263953] r10:00000000 r9:ec936000 r8:7ecf1b74 r7:4024700a r6:ed1e9c80 r5:00000003 [ 82.271869] r4:ed1e9c80 [ 82.274432] [<802849fc>] (SyS_ioctl) from [<80108520>] (ret_fast_syscall+0x0/0x1c) [ 82.282005] r9:ec936000 r8:801086c4 r7:00000036 r6:00000000 r5:00000003 r4:0008e1bc root@GE004097290448 b850v3:~# Message from syslogd@GE004097290448 at Dec 3 11:17:08 ... kernel:[ 82.108175] BUG: spinlock wrong CPU on CPU#0, hwclock/855 Message from syslogd@GE004097290448 at Dec 3 11:17:08 ... kernel:[ 82.113660] lock: 0xedb4899c, .magic: dead4ead, .owner: hwclock/855, .owner_cpu: 1 hwclock --systohc root@GE004097290448 b850v3:~# Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.co.uk> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
* | Merge tag 'pinctrl-v4.11-1' of ↵Linus Torvalds2017-02-221-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Pin control bulk changes for the v4.11 kernel cycle. Core changes: - Switch the generic pin config argument from 16 to 24 bits, only use 8 bits for the configuration type. We might need to encode more information about a certain setting than we need to encode different generic settings. - Add a cross-talk API to the pin control GPIO back-end, utilizing pinctrl_gpio_set_config() from GPIO drivers that want to set up a certain pin configuration in the back-end. This also includes the .set_config() refactoring of the GPIO chips, so that they pass a generic configuration for things like debouncing and single ended (typically open drain). This change has also been merged in an immutable branch to the GPIO tree. - Take hogs with a delayed work, so that we finalize probing a pin controller before trying to get any hogs. - For pin controllers putting all group and function definitions into the device tree, we now have generic code to deal with this and it is used in two drivers so far. - Simplifications of the pin request conflict check. - Make dt_free_map() optional. Updates to drivers: - pinctrl-single now use the generic helpers to generate dynamic group and function tables from the device tree. - Texas Instruments IOdelay configuration driver add-on to pinctrl-single. - i.MX: use radix trees to store groups and functions, use the new generic group and function helpers to manage them. - Intel: add support for hardware debouncing and 1K pull-down. New subdriver for the Gemini Lake SoC. - Renesas SH-PFC: drive strength and bias support, CAN bus muxing, MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791. - Aspeed: use syscon cross-dependencies to set up related bits in the LPC host controller and display controller. - Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs. Add banks Y, Z, AA, AB and AC. - AMD: support additional GPIO. - STM32: set this controller to strict muxing mode. STM32H743 MCU support. - Allwinner sunxi: deep simplifications on how to support subvariants of SoCs without adding to much SoC-specific data for each subvariant, especially for sun5i variants. New driver for V3s SoCs. New driver for the H5 SoC. Support A31/A31s variants with the new variant framework. - Mvebu: simplifications to use a MMIO and regmap abstraction. New subdrivers for the 98DX3236, 98DX5241 SoCs. - Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC driver to access regmaps. Add infrastructure for pin-bank retention control. Clean out the pin retention control from arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in the Samsung pin control driver(s). - Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin. - Qualcomm: use raw spinlock variants: this makes the qualcomm driver realtime-safe" * tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits) pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data() pinctrl: intel: unlock on error in intel_config_set_pull() pinctrl: berlin: make bool drivers explicitly non-modular pinctrl: spear: make bool drivers explicitly non-modular pinctrl: mvebu: make bool drivers explicitly non-modular pinctrl: sunxi: make sun5i explicitly non-modular pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function pinctrl: samsung: mark PM functions as __maybe_unused pinctrl: sunxi: Remove redundant A31s pinctrl driver pinctrl: sunxi: Support A31/A31s with pinctrl variants pinctrl: Amend bindings for STM32 pinctrl pinctrl: Add STM32 pinctrl driver DT bindings pinctrl: stm32: Add STM32H743 MCU support include: dt-bindings: Add STM32H7 pinctrl DT defines gpio: aspeed: Remove dependence on GPIOF_* macros pinctrl: stm32: fix bad location of gpiochip_lock_as_irq drivers: pinctrl: add driver for Allwinner H5 SoC pinctrl: intel: Add Intel Gemini Lake pin controller support pinctrl: intel: Add support for 1k additional pull-down pinctrl: intel: Add support for hardware debouncer ...
| * | pinctrl: Widen the generic pinconf argument from 16 to 24 bitsMika Westerberg2017-01-261-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current pinconf packed format allows only 16-bit argument limiting the maximum value 65535. For most types this is enough. However, debounce time can be in range of hundreths of milliseconds in case of mechanical switches so we cannot represent the worst case using the current format. In order to support larger values change the packed format so that the lower 8 bits are used as type which leaves 24 bits for the argument. This allows representing values up to 16777215 and debounce times up to 16 seconds. We also convert the existing users to use 32-bit integer when extracting argument from the packed configuration value. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* / rtc: jz4740: make the driver buildable as a module againAlexandre Belloni2017-01-262-3/+14
|/ | | | | | | | | | | | | | By using kernel_halt() instead of machine_halt(), we can make the driver build as a module. However, jz4740 platforms not loading this module will not be able to power off. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Revert "rtc: jz4740: make the driver builtin only" This reverts commit b9168c539c0b2de756aaffd380384dbde8adbe07.
* ktime: Cleanup ktime_set() usageThomas Gleixner2016-12-251-4/+4
| | | | | | | | | | ktime_set(S,N) was required for the timespec storage type and is still useful for situations where a Seconds and Nanoseconds part of a time value needs to be converted. For anything where the Seconds argument is 0, this is pointless and can be replaced with a simple assignment. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
* ktime: Get rid of the unionThomas Gleixner2016-12-251-4/+4
| | | | | | | | | | | | | | | ktime is a union because the initial implementation stored the time in scalar nanoseconds on 64 bit machine and in a endianess optimized timespec variant for 32bit machines. The Y2038 cleanup removed the timespec variant and switched everything to scalar nanoseconds. The union remained, but become completely pointless. Get rid of the union and just keep ktime_t as simple typedef of type s64. The conversion was done with coccinelle and some manual mopping up. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
* Merge tag 'rtc-4.10' of ↵Linus Torvalds2016-12-1914-159/+975
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC updates from Alexandre Belloni: "Subsystem: - non-modular drivers are now explicitly non-modular New driver: - Epson Toyocom rtc-7301sf/dg Drivers: - cmos: reject unsupported alarm values wrt the RTC capabilities - ds1307: ACPI support - jz4740: DT support, jz4780 handling, can now be used as a system power controller - mcp795: many fixes, in particular proper month handling - twl: driver is now DT only" * tag 'rtc-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (31 commits) rtc: mcp795: Fix whitespace and indentation. rtc: mcp795: Prefer using the BIT() macro. rtc: mcp795: fix month write resetting date to 1. rtc: mcp795: fix time range difference between linux and RTC chip. rtc: mcp795: fix bitmask value for leap year (LP). rtc: mcp795: use bcd2bin/bin2bcd. rtc: add support for EPSON TOYOCOM RTC-7301SF/DG rtc: ds1307: Add ACPI support rtc: imxdi: (trivial) fix a typo rtc: ds1374: Merge conditional + WARN_ON() rtc: twl: make driver DT only rtc: twl: kill static variables rtc: fix typos in Kconfig rtc: jz4740: make the driver builtin only rtc: jz4740: remove unused EXPORT_SYMBOL Documentation: bindings: fix twl-rtc documentation rtc: Enable compile testing for Maxim and Samsung drivers MIPS: jz4740: Remove obsolete code MIPS: qi_lb60: Probe RTC driver from DT and use it as power controller MIPS: jz4740: DTS: Probe the jz4740-rtc driver from devicetree ...
| * rtc: mcp795: Fix whitespace and indentation.Emil Bartczak2016-12-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | Fix whitespace and indentation errors and the following checkpatch warnings: - line 15: Block comments use a trailing */ on a separate line - line 256: Line over 80 characters No code change. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: mcp795: Prefer using the BIT() macro.Emil Bartczak2016-12-191-2/+2
| | | | | | | | | | | | | | | | This patch doesn't change the code but replaces all bitmask values with the BIT(x) macro. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: mcp795: fix month write resetting date to 1.Emil Bartczak2016-12-191-5/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Microchip errata some combinations of date and month values may result in the date being reset to 1, even if the date is also written with the month (for example 31-07 or 31-08). As a workaround avoid writing date and month values within the same Write command. Instead, terminate the Write command after loading the date and begin a new command to write the month. In addition, disable the oscillator before loading the new values. This is done by ensuring both the ST and EXTOSC bits are cleared and waiting for the OSCON bit to clear. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * rtc: mcp795: fix time range difference between linux and RTC chip.Emil Bartczak2016-12-191-2/+2
| | | | | | | | | | | | | | | | In linux rtc_time struct, tm_mon range is 0~11, while in RTC HW REG, month range is 1~12. This patch adjusts difference of them. Signed-off-by: Emil Bartczak <emilbart@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 05:49:33 +0100