| Commit message (Expand) | Author | Files | Lines | |
|---|---|---|---|---|
| 2018-04-16 | clk: renesas: r8a77980: Correct parent clock of PCIEC0 | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: r8a7794: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: r8a7792: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: r8a7791/r8a7793: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: r8a7745: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: r8a7743: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-04-16 | clk: renesas: cpg-mssr: Add r8a77470 support | Biju Das | 7 | -3/+260 |
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