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* Merge tag 'imx-drivers-5.20' of ↵Arnd Bergmann2022-07-122-5/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers change for 5.20: - Update imx8m-blk-ctrl driver to print the name of the power domain, so that the error message becomes more useful. - Update the error messages in gpcv2 driver by printing the reason why a regulator fails to be enabled or disabled. - A series from Michael Walle to convert the guts driver from a platform driver to an core_initcall for getting rid of all those global static variables. - A couple of follow-up fixes on guts driver series. * tag 'imx-drivers-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: fsl: guts: check return value after calling of_iomap() in fsl_guts_get_soc_uid() soc: fsl: guts: fix return value check in fsl_guts_init() soc: imx: imx8m-blk-ctrl: Make error prints useful soc: fsl: guts: add serial_number support soc: fsl: guts: drop platform driver soc: fsl: guts: use of_root instead of own reference soc: fsl: guts: allocate soc_dev_attr on the heap soc: fsl: guts: embed fsl_guts_get_svr() in probe() soc: fsl: guts: remove module_exit() and fsl_guts_remove() soc: fsl: guts: machine variable might be unset soc: imx: gpcv2: print errno for regulator errors Link: https://lore.kernel.org/r/20220709082951.15123-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * soc: imx: imx8m-blk-ctrl: Make error prints usefulMarek Vasut2022-06-271-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Print the name of the power domain which failed to make the error prints actually useful for finding the error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexander Stein <alexander.stein@ew.tq-group.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Martyn Welch <martyn.welch@collabora.com> Cc: Paul Elder <paul.elder@ideasonboard.com> Cc: Shawn Guo <shawnguo@kernel.org> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: print errno for regulator errorsMartin Kepplinger2022-06-191-2/+6
| | | | | | | | | | | | | | | | Make debugging of power management issues easier by printing the reason why a regulator fails to be enabled or disabled. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | soc: imx: imx8m-blk-ctrl: fix display clock for LCDIF2 power domainAlexander Stein2022-06-141-1/+1
|/ | | | | | | | | | LCDIF2 has its own display clock, use this one. Fixes: 07614fed00e9 ("soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Paul Elder <paul.elder@ideasonboard.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'arm-drivers-5.19' of ↵Linus Torvalds2022-05-264-14/+1237
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are minor updates to SoC specific drivers for chips by Rockchip, Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy driver changes include: - Several conversions of DT bindings to yaml format. - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs. - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core), and support for more chips in the RPMh power domains and the soc-id. - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP. - Apple M1 gains support for the on-chip NVMe controller, making it possible to finally use the internal disks. This also includes SoC drivers for their RTKit IPC and for the SART DMA address filter. For other subsystems that merge their drivers through the SoC tree, we have - Firmware drivers for the ARM firmware stack including TEE, OP-TEE, SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE now has a cache for firmware argument structures as an optimization, and SCMI now supports the 3.1 version of the specification. - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers - Memory controller updates for Tegra, and a few updates for other platforms" * tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits) memory: tegra: Add MC error logging on Tegra186 onward memory: tegra: Add memory controller channels support memory: tegra: Add APE memory clients for Tegra234 memory: tegra: Add Tegra234 support nvme-apple: fix sparse endianess warnings soc/tegra: pmc: Document core domain fields soc: qcom: pdr: use static for servreg_* variables soc: imx: fix semicolon.cocci warnings soc: renesas: R-Car V3U is R-Car Gen4 soc: imx: add i.MX8MP HDMI blk-ctrl soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl soc: imx: add i.MX8MP HSIO blk-ctrl soc: imx: imx8m-blk-ctrl: set power device name soc: qcom: llcc: Add sc8180x and sc8280xp configurations dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles soc/tegra: pmc: Select REGMAP dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml ...
| * soc: imx: fix semicolon.cocci warningskernel test robot2022-05-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/soc/imx/imx8mp-blk-ctrl.c:227:61-62: Unneeded semicolon drivers/soc/imx/imx8mp-blk-ctrl.c:192:61-62: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 556f5cf9568a ("soc: imx: add i.MX8MP HSIO blk-ctrl") CC: Lucas Stach <l.stach@pengutronix.de> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: add i.MX8MP HDMI blk-ctrlLucas Stach2022-05-051-0/+193
| | | | | | | | | | | | | | | | This adds driver support for the HDMI blk-ctrl found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrlPaul Elder2022-05-051-2/+121
| | | | | | | | | | | | | | | | | | | | | | | | Add the description for the i.MX8MP media blk-ctrl. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1 and #2 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: add i.MX8MP HSIO blk-ctrlLucas Stach2022-05-052-0/+504
| | | | | | | | | | | | | | | | | | | | The i.MX8MP added some blk-ctrl peripherals that don't follow the regular structure of the blk-ctrls in the previous SoCs. Add a new file for those with currently only the HSIO blk-ctrl being supported. Others will be added later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: imx8m-blk-ctrl: set power device nameLucas Stach2022-05-051-0/+1
| | | | | | | | | | | | | | | | | | Set the name for the virtual power device to the name of the attached blk-ctrl domain. Makes the debug output for the power domains a lot more pleasant to read. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: add support for i.MX8MP power domainsLucas Stach2022-04-081-1/+386
| | | | | | | | | | | | | | | | | | | | | | This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: add PGC control register indirectionLucas Stach2022-04-081-11/+32
| | | | | | | | | | | | | | | | | | | | | | The PGC control registers in the shared (not per-PGC) region of the GPC address space have different offsets on i.MX8MP to make space for additional interrupt control registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | soc: imx: imx8m-blk-ctrl: Fix IMX8MN_DISPBLK_PD_ISI hangAdam Ford2022-04-101-1/+1
|/ | | | | | | | | | | The imx8mn clock list for the ISI lists four clocks, but DOMAIN_MAX_CLKS was set to 3. Because of this, attempts to enable the fourth clock failed, threw some splat, and ultimately hung. Fixes: 7f511d514e8c ("soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'arm-drivers-5.18' of ↵Linus Torvalds2022-03-242-3/+66
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are a few separately maintained driver subsystems that we merge through the SoC tree, notable changes are: - Memory controller updates, mainly for Tegra and Mediatek SoCs, and clarifications for the memory controller DT bindings - SCMI firmware interface updates, in particular a new transport based on OPTEE and support for atomic operations. - Cleanups to the TEE subsystem, refactoring its memory management For SoC specific drivers without a separate subsystem, changes include - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP Layerscape SoCs. - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L, and Qualcomm SM8450. - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older NVIDIA Tegra chips" * tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits) ARM: spear: fix typos in comments soc/microchip: fix invalid free in mpfs_sys_controller_delete soc: s4: Add support for power domains controller dt-bindings: power: add Amlogic s4 power domains bindings ARM: at91: add support in soc driver for new SAMA5D29 soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC memory: emif: check the pointer temp in get_device_details() memory: emif: Add check for setup_interrupts dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: ti: k3-socinfo: Add AM62x JTAG ID soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 ...
| * soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrlLucas Stach2022-02-111-0/+66
| | | | | | | | | | | | | | | | | | This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: Remove Layerscape checkFabio Estevam2022-01-281-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 4ebd29f91629 ("soc: imx: Register SoC device only on i.MX boards") the soc-imx driver is only registered on i.MX platforms as intended. This means that we no longer need to do a specific check for Layerscape. Remove the now unneeded "fsl,ls1021a" check. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | soc: imx: gpcv2: Fix clock disabling imbalance in error pathLaurent Pinchart2022-02-211-1/+2
|/ | | | | | | | | | | | | The imx_pgc_power_down() starts by enabling the domain clocks, and thus disables them in the error path. Commit 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") made the clock enable conditional, but forgot to add the same condition to the error path. This can result in a clock enable/disable imbalance. Fix it. Fixes: 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'drivers-5.17' of ↵Linus Torvalds2022-01-102-2/+104
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are cleanups and minor bugfixes across several SoC specific drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone, Renesas, ZynqMP Noteworthy new features are: - The op-tee firmware driver gains support for asynchronous notifications from secure-world firmware. - Qualcomm platforms gain support for new SoC types in various drivers: power domain, cache controller, RPM sleep, soc-info - Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as well as a new USIv2 driver that handles various types of serial communiction (uart, i2c, spi) - Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers, as well as memory controller support for RZ/G2L (R9A07G044). - Apple M1 gains support for the PMGR power management driver" * tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ...
| * soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrlAdam Ford2021-12-171-1/+76
| | | | | | | | | | | | | | | | This adds the description for the i.MX8MN disp blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: Add dispmix and mipi domains to imx8mnAdam Ford2021-12-171-0/+25
| | | | | | | | | | | | | | | | | | The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabledAdam Ford2021-12-171-0/+1
| | | | | | | | | | | | | | | | | | Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock activeAdam Ford2021-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | Enable the vpu-h1 clock when the domain is active because reading or writing to the VPU-H1 IP block cause the system to hang. Fixes: 656ade7aa42a ("soc: imx: gpcv2: keep i.MX8M* bus clocks enabled") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: Synchronously suspend MIX domainsMarek Vasut2021-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the following power domain sequence happens, iMX8M Mini always hangs: gpumix:on -> gpu:on -> gpu:off -> gpu:on This is likely due to another quirk of the GPC block. This situation can be prevented by always synchronously powering off both the domain and MIX domain. Make it so. This turns the aforementioned sequence into: gpumix:on -> gpu:on -> gpu:off -> gpumix:off -> gpumix:on -> gpu:on Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | soc: imx: Register SoC device only on i.MX boardsStephan Gerhold2021-12-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, using the ARM32 multi_v7_defconfig always results in two SoCs being exposed in sysfs. This is wrong, as far as I'm aware the Qualcomm DragonBoard 410c does not actually make use of a i.MX SoC. :) qcom-db410c:/sys/devices/soc0$ grep . * family:Freescale i.MX machine:Qualcomm Technologies, Inc. APQ 8016 SBC revision:0.0 serial_number:0000000000000000 soc_id:Unknown qcom-db410c:/sys/devices/soc1$ grep . * family:Snapdragon machine:APQ8016 ... This happens because imx_soc_device_init() registers the soc device unconditionally, even when running on devices that do not make use of i.MX. Arnd already reported this more than a year ago and even suggested a fix similar to this commit, but for some reason it was never submitted. Fix it by checking if the "__mxc_cpu_type" variable was actually initialized by earlier platform code. On devices without i.MX it will simply stay 0. Cc: Peng Fan <peng.fan@nxp.com> Fixes: d2199b34871b ("ARM: imx: use device_initcall for imx_soc_device_init") Reported-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/CAK8P3a0hxO1TmK6oOMQ70AHSWJnP_CAq57YMOutrxkSYNjFeuw@mail.gmail.com/ Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi resetAdam Ford2021-12-061-0/+19
|/ | | | | | | | | | | | | | | | | Most of the blk-ctrl reset bits are found in one register, however there are two bits in offset 8 for pulling the MIPI DPHY out of reset and one of them needs to be set when IMX8MM_DISPBLK_PD_MIPI_CSI is brought out of reset or the MIPI_CSI hangs. Since MIPI_DSI is impacted, add the additional one for MIPI_DSI too. Fixes: 926e57c065df ("soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate()Dan Carpenter2021-10-151-1/+1
| | | | | | | | | | | The > comparison should be >= to prevent reading one element beyond the end of the array. The onecell_data->domains[] array is allocated in imx8m_blk_ctrl_probe() and it has "onecell_data->num_domains" elements. Fixes: 5b340e7813d4 ("soc: imx: add i.MX8M blk-ctrl driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: imx8m-blk-ctrl: add DISP blk-ctrlLucas Stach2021-10-061-0/+70
| | | | | | | | This adds the description for the i.MX8MM disp blk-ctrl. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: add i.MX8M blk-ctrl driverLucas Stach2021-10-062-0/+454
| | | | | | | | | | | | | | | | | | | | | | | This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX power domains and interacts with the GPC power controller to provide the peripherals in the power domain access to the NoC and ensures that those peripherals are properly reset when their respective power domain is brought back to life. Software needs to do different things to make the bus handshake happen after the GPC *MIX domain is powered up and before it is powered down. As the requirements are quite different between the various blk-ctrls there is a callback function provided to hook in the proper sequence. The peripheral domains are quite uniform, they handle the soft clock enables and resets in the blk-ctrl address space and sequencing with the upstream GPC power domains. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: support system suspend/resumeLucas Stach2021-10-061-0/+31
| | | | | | | | | | | | | | | | | Our usage of runtime PM to control the hierarchy of power domains is slightly unusual and means that powering up a domain may fail in early system resume, as runtime PM is still disallowed at this stage. However the system suspend/resume path takes care of powering down/up the power domains in the order defined by the device parent/child and power-domain provider/consumer hierarachy. So we can just runtime resume all our power-domain devices to allow the power-up to work properly in the resume path. System suspend will still disable all domains as intended. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: keep i.MX8M* bus clocks enabledLucas Stach2021-10-061-0/+6
| | | | | | | | | Annotate the domains with bus clocks to keep those clocks enabled as long as the domain is active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add domain option to keep domain clocks enabledLucas Stach2021-10-061-5/+9
| | | | | | | | | | | | Some of the MIX domains are using clocks to drive the bus bridges. Those must be enabled at all times, as long as the domain is powered up and they don't have any other consumer than the power domain. Add an option to keep the clocks attached to a domain enabled as long as the domain is power up and only disable them after the domain is powered down. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: add lockdep annotationLucas Stach2021-10-061-0/+4
| | | | | | | | | | | | | Some of the GPCv2 power domains are nested inside each other without visibility to lockdep at the genpd level, as they are in separate driver instances and don't have a parent/child power-domain relationship. Add a subclass annotation to the nested domains to let lockdep know that it is okay to take the genpd lock in a nested fashion. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"Lucas Stach2021-10-051-2/+2
| | | | | | | | | | | | | | This reverts commit a77ebdd9f553. It turns out that the VPU domain has no different requirements, even though the downstream ATF implementation seems to suggest otherwise. Powering on the domain with the reset asserted works fine. As the changed sequence has caused sporadic issues with the GPU domains, just revert the change to go back to the working sequence. Cc: <stable@vger.kernel.org> # 5.14 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Peng Fan <peng.fan@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: allow to disable individual power domainsLucas Stach2021-10-051-0/+3
| | | | | | | | | | | | | | Some board designs don't supply power to all of the power domains, as they are not used anyways. In that case we must make sure to not touch those power domains at all, as trying to power up a domain that has no power supplied to it will obviously end in a system crash. Allow to disable those domains via the standard DT status property. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-By: Tim Harvey <tharvey@gateworks.com> Tested-By: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* imx: soc: Select REGMAP_MMIOEzequiel Garcia2021-10-051-0/+1
| | | | | | | | | | | | | | | The imx-gpcv2 driver needs Regmap MMIO. Select it, and fix: drivers/soc/imx/gpcv2.c:420:34: error: array type has incomplete element type ‘struct regmap_range’ 420 | static const struct regmap_range imx7_yes_ranges[] = { | ^~~~~~~~~~~~~~~ drivers/soc/imx/gpcv2.c:421:17: error: implicit declaration of function ‘regmap_reg_range’; did you mean ‘remap_pfn_range’? [-Werror=implicit-function-declaration] 421 | regmap_reg_range(GPC_LPCR_A_CORE_BSC, | ^~~~~~~~~~~~~~~~ | remap_pfn_range Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domainMarek Vasut2021-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | To bring up the MX8MM GPU domain, it is necessary to configure both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without this configuration, the system might hang on boot when bringing up the GPU power domain. This is sporadically observed on multiple disparate systems. Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are configured when bringing up the GPU domain. This fixes the sporadic hang. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* soc: imx: gpcv2: Turn domain->pgc into bitfieldMarek Vasut2021-10-041-34/+38
| | | | | | | | | | | | | | | | | | | | | | | There is currently the MX8MM GPU domain, which is in fact a composite domain for both GPU2D and GPU3D. To correctly configure this domain, it is necessary to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. Turn the domain->pgc from value into bitfield and use for_each_set_bit() to iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL register array. This way it is possible to configure all GPC_PGC_nCTRL registers required in a particular domain. This is a preparatory patch, no functional change. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Revert "soc: imx8m: change to use platform driver"Lucas Stach2021-07-151-72/+12
| | | | | | | | | | | | | | | With the SoC matching changed to a platform driver the match data is available only after other drivers, which may rely on it are already probed. This breaks at least the CAAM driver on i.MX8M. Revert the change until all those drivers have been audited and changed to be able to eal with match data being available later in the boot process. Fixes: 7d981405d0fd ("soc: imx8m: change to use platform driver") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'arm-drivers-5.14' of ↵Linus Torvalds2021-07-101-115/+519
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Olof Johansson: - Reset controllers: Adding support for Microchip Sparx5 Switch. - Memory controllers: ARM Primecell PL35x SMC memory controller driver cleanups and improvements. - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN. - Rockchip: RK3568 power domains support + DT binding updates, cleanups. - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details, including support for MSM8226, MDM9607, SM6125 and SC8180X. - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management interfaces and communication (including bus model) between partitions both in Normal and Secure Worlds. - Tegra Memory controller changes, including major rework to deal with identity mappings at boot and integration with ARM SMMU pieces. * tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (120 commits) firmware: turris-mox-rwtm: add marvell,armada-3700-rwtm-firmware compatible string firmware: turris-mox-rwtm: show message about HWRNG registration firmware: turris-mox-rwtm: fail probing when firmware does not support hwrng firmware: turris-mox-rwtm: report failures better firmware: turris-mox-rwtm: fix reply status decoding function soc: imx: gpcv2: add support for i.MX8MN power domains dt-bindings: add defines for i.MX8MN power domains firmware: tegra: bpmp: Fix Tegra234-only builds iommu/arm-smmu: Use Tegra implementation on Tegra186 iommu/arm-smmu: tegra: Implement SID override programming iommu/arm-smmu: tegra: Detect number of instances at runtime dt-bindings: arm-smmu: Add Tegra186 compatible string firmware: qcom_scm: Add MDM9607 compatible soc: qcom: rpmpd: Add MDM9607 RPM Power Domains soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml memory: emif: remove unused frequency and voltage notifiers memory: fsl_ifc: fix leak of private memory on probe failure memory: fsl_ifc: fix leak of IO mapping on probe failure ...
| * soc: imx: gpcv2: add support for i.MX8MN power domainsAdam Ford2021-06-121-0/+92
| | | | | | | | | | | | | | | | | | | | | | This adds support for the power domains founds on i.MX8MN. The Nano has fewer domains than the Mini, and the access to some of these domains is different than that of the Mini, the Mini power domains cannot be reused. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: move reset assert after requesting domain power upPeng Fan2021-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8MM VPU power up sequence is a bit special, it must follow: 1. request power up 2. reset assert 3. reset deassert This change in this patch will not affect other domains, because the power domain default is in asserted state, unless bootloader deassert the reset. It also applies to GPU power domain. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX power domainsLucas Stach2021-05-271-0/+70
| | | | | | | | | | | | | | | | | | | | With the BLK-CTL driver now in place, let's add the missing domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: add support for i.MX8MM power domainsLucas Stach2021-05-271-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the power domains found on i.MX8MM. The 2D and 3D GPU domains are abstracted as a single domain in the driver, as they can't be powered up/down individually due to a shared reset. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: add support for optional resetsLucas Stach2021-05-231-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: allow domains without power-sequence controlLucas Stach2021-05-231-40/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | Some of the PGC domains only control the handshake with the ADB400 and don't have any power sequence controls. Make such domains work by allowing the pxx and map bits to be empty and skip all actions using those controls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: add runtime PM support for power-domainsLucas Stach2021-05-231-1/+17
| | | | | | | | | | | | | | | | | | | | | | This allows to nest domains into other power domains and have the parent domain powered up/down as required by the child domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: wait for ADB400 handshakeLucas Stach2021-05-231-8/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New reference manuals show that there is actually a status bit for the ADB400 handshake. Add a poll loop to wait for the ADB400 to acknowledge our request. [Peng Fan: i.MX8MM has blk ctl module, the handshake can only finish after setting blk ctl. The blk ctl driver will set the bus clk bit and the handshake will finish there. we just add a delay and suppose the handshake will finish after that.] Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: split power up and power down sequence controlLucas Stach2021-05-231-55/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current mixed function to control both power up and power down sequences is very hard to follow and already contains some sequence errors like triggering the ADB400 handshake at the wrong time due to this. Split the function into two, which results in slightly more code, but is way easier to get right. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: switch to clk_bulk_* APILucas Stach2021-05-231-48/+12
| | | | | | | | | | | | | | | | | | | | | | Use clk_bulk API to simplify the code a bit. Also add some error checking to the clk_prepare_enable calls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * soc: imx: gpcv2: move domain mapping to domain driver probeLucas Stach2021-05-231-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | As long as the power domain driver is active we want power control over the domain (which is what the mapping bit requests), so there is no point in whacking it for every power control action, simply set the bit in driver probe and clear it when the driver is removed. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 11:11:21 +0100