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* soc: rockchip: dtpm: use C99 array init syntaxRandy Dunlap2023-06-111-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | Eliminate sparse warnings in soc/rockchip/dtpm.c: drivers/soc/rockchip/dtpm.c:15:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:17:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:20:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:23:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:26:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:29:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:32:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:35:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:38:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:41:12: sparse: warning: obsolete array initializer, use C99 syntax Fixes: b9d6c47a2be8 ("rockchip/soc/drivers: Add DTPM description for rk3399") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-rockchip@lists.infradead.org Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230501024950.31518-1-rdunlap@infradead.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: add rk3588 mem module supportBoris Brezillon2023-05-071-35/+125
| | | | | | | | | | | | | | On RK3588 it's also possible to power down the memory used by the particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds support for this feature. Tested-by: Vincent Legoll <vincent.legoll@gmail.com> Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230403193250.108693-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: add power domain support for rk3588Finley Xiao2022-09-091-4/+87
| | | | | | | | | | This driver is modified to support RK3588 SoCs. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [port of downstream code incl. merging in fixes] Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220906143825.199089-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: do not enable domain when adding itElaine Zhang2022-09-091-9/+1
| | | | | | | | | | It's not need to power on all pd when add pm domain. Instead use PD's real status in pm_genpd_init(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220906143825.199089-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: io-domain: Add RV1126 IO domainsJianqun Xu2022-09-051-0/+20
| | | | | | | | | | | Add IO domains support for RV1126 SoC. Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220818124132.125304-6-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: Add RV1126 power domainsJagan Teki2022-09-051-0/+29
| | | | | | | | | | | Add power domains support for RV1126 SoC. Cypto, VO and NPU domains will add it future patches. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220818124132.125304-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'v5.19-rockchip-drivers2' of ↵Arnd Bergmann2022-05-271-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/late Refcount leak for a used of-node in the grf-init. * tag 'v5.19-rockchip-drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: Fix refcount leak in rockchip_grf_init Link: https://lore.kernel.org/r/4541398.Icojqenx9y@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * soc: rockchip: Fix refcount leak in rockchip_grf_initMiaoqian Lin2022-05-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | of_find_matching_node_and_match returns a node pointer with refcount incremented, we should use of_node_put() on it when done. Add missing of_node_put() to avoid refcount leak. Fixes: 4c58063d4258 ("soc: rockchip: add driver handling grf setup") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220516072013.19731-1-linmq006@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'arm-drivers-5.19' of ↵Linus Torvalds2022-05-263-17/+34
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are minor updates to SoC specific drivers for chips by Rockchip, Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy driver changes include: - Several conversions of DT bindings to yaml format. - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs. - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core), and support for more chips in the RPMh power domains and the soc-id. - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP. - Apple M1 gains support for the on-chip NVMe controller, making it possible to finally use the internal disks. This also includes SoC drivers for their RTKit IPC and for the SART DMA address filter. For other subsystems that merge their drivers through the SoC tree, we have - Firmware drivers for the ARM firmware stack including TEE, OP-TEE, SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE now has a cache for firmware argument structures as an optimization, and SCMI now supports the 3.1 version of the specification. - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers - Memory controller updates for Tegra, and a few updates for other platforms" * tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits) memory: tegra: Add MC error logging on Tegra186 onward memory: tegra: Add memory controller channels support memory: tegra: Add APE memory clients for Tegra234 memory: tegra: Add Tegra234 support nvme-apple: fix sparse endianess warnings soc/tegra: pmc: Document core domain fields soc: qcom: pdr: use static for servreg_* variables soc: imx: fix semicolon.cocci warnings soc: renesas: R-Car V3U is R-Car Gen4 soc: imx: add i.MX8MP HDMI blk-ctrl soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl soc: imx: add i.MX8MP HSIO blk-ctrl soc: imx: imx8m-blk-ctrl: set power device name soc: qcom: llcc: Add sc8180x and sc8280xp configurations dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles soc/tegra: pmc: Select REGMAP dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml ...
| * soc: rockchip: power-domain: Replace dsb() with smb()Brian Norris2022-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's unclear if these are really needed at all, but seemingly their purpose is only as a write barrier. Use the general macro instead of the ARM-specific one. This driver is partially marked for COMPILE_TEST'ing, but it doesn't build under non-ARM architectures. Fix this up before *really* enabling it for COMPILE_TEST. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220426014545.628100-2-briannorris@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: Clean up Kconfig whitespaceBrian Norris2022-04-301-12/+12
| | | | | | | | | | | | | | | | | | There are spaces instead of tabs, and other inconsistent indentation. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220426014545.628100-1-briannorris@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: set dwc3 clock for rk3566Peter Geis2022-04-101-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to the combophy as the clock source. As combophy0 doesn't exist on rk3566, we need to set the clock source to the usb2 phy instead. Add handling to the grf driver to handle this on boot. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: pm_domains: Fix typo in commentSebastian Fricke2022-04-101-3/+3
| | | | | | | | | | | | | | | | s/eject devices form power domain/eject devices from the power domain/ Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Link: https://lore.kernel.org/r/20220326183451.66115-1-sebastian.fricke@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | soc: rockchip: power-domain: Manage resource conflicts with firmwareBrian Norris2022-05-081-0/+118
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On RK3399 platforms, power domains are managed mostly by the kernel (drivers/soc/rockchip/pm_domains.c), but there are a few exceptions where ARM Trusted Firmware has to be involved: (1) system suspend/resume (2) DRAM DVFS (a.k.a., "ddrfreq") Exception (1) does not cause much conflict, since the kernel has quiesced itself by the time we make the relevant PSCI call. Exception (2) can cause conflict, because of two actions: (a) ARM Trusted Firmware needs to read/modify/write the PMU_BUS_IDLE_REQ register to idle the memory controller domain; the kernel driver also has to touch this register for other domains. (b) ARM Trusted Firmware needs to manage the clocks associated with these domains. To elaborate on (b): idling a power domain has always required ungating an array of clocks; see this old explanation from Rockchip: https://lore.kernel.org/linux-arm-kernel/54503C19.9060607@rock-chips.com/ Historically, ARM Trusted Firmware has avoided this issue by using a special PMU_CRU_GATEDIS_CON0 register -- this register ungates all the necessary clocks -- when idling the memory controller. Unfortunately, we've found that this register is not 100% sufficient; it does not turn the relevant PLLs on [0]. So it's possible to trigger issues with something like the following: 1. enable a power domain (e.g., RK3399_PD_VDU) -- kernel will temporarily enable relevant clocks/PLLs, then turn them back off 2. a PLL (e.g., PLL_NPLL) is part of the clock tree for RK3399_PD_VDU's clocks but otherwise unused; NPLL is disabled 3. perform a ddrfreq transition (rk3399_dmcfreq_target() -> ... drivers/clk/rockchip/clk-ddr.c / ROCKCHIP_SIP_DRAM_FREQ) 4. ARM Trusted Firmware unagates VDU clocks (via PMU_CRU_GATEDIS_CON0) 5. ARM Trusted firmware idles the memory controller domain 6. Step 5 waits on the VDU domain/clocks, but NPLL is still off i.e., we hang the system. So for (b), we need to at a minimum manage the relevant PLLs on behalf of firmware. It's easier to simply manage the whole clock tree, in a similar way we do in rockchip_pd_power(). For (a), we need to provide mutual exclusion betwen rockchip_pd_power() and firmware. To resolve that, we simply grab the PMU mutex and release it when ddrfreq is done. The Chromium OS kernel has been carrying versions of part of this hack for a while, based on some new custom notifiers [1]. I've rewritten as a simple function call between the drivers, which is OK because: * the PMU driver isn't enabled, and we don't have this problem at all (the firmware should have left us in an OK state, and there are no runtime conflicts); or * the PMU driver is present, and is a single instance. And the power-domain driver cannot be removed, so there's no lifetime management to worry about. For completeness, there's a 'dmc_pmu_mutex' to guard (likely theoretical?) probe()-time races. It's OK for the memory controller driver to start running before the PMU, because the PMU will avoid any critical actions during the block() sequence. [0] The RK3399 TRM for PMU_CRU_GATEDIS_CON0 only talks about ungating clocks. Based on experimentation, we've found that it does not power up the necessary PLLs. [1] CHROMIUM: soc: rockchip: power-domain: Add notifier to dmc driver https://chromium-review.googlesource.com/q/I242dbd706d352f74ff706f5cbf42ebb92f9bcc60 Notably, the Chromium solution only handled conflict (a), not (b). In practice, item (b) wasn't a problem in many cases because we never managed to fully power off PLLs. Now that the (upstream) video decoder driver performs runtime clock management, we often power off NPLL. Signed-off-by: Brian Norris <briannorris@chromium.org> Tested-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
* dtpm/soc/rk3399: Add the ability to unload the moduleDaniel Lezcano2022-02-231-0/+6
| | | | | | | | | | | The dtpm hierarchy can now be removed with the dtpm_destroy_hierarchy() function. Add the module_exit() callback so the module can be unloaded by removing the previously created hierarchy. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20220130210210.549877-7-daniel.lezcano@linaro.org
* rockchip/soc/drivers: Add DTPM description for rk3399Daniel Lezcano2022-02-043-0/+68
| | | | | | | | | | | | | | | | | | | | | | The DTPM framework does support now the hierarchy description. The platform specific code can call the hierarchy creation function with an array of struct dtpm_node pointing to their parent. This patch provides a description of the big / Little CPUs and the GPU and tie them together under a virtual 'package' name. Only rk3399 is described now. The description could be extended in the future with the memory controller with devfreq. The description is always a module and it describes the soft dependencies. The userspace has to load the softdeps module in the right order. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by; Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220128163537.212248-6-daniel.lezcano@linaro.org
* soc: rockchip: io-domain: Remove unneeded semicolonJiapeng Chong2021-08-191-1/+1
| | | | | | | | | | | Fix the following coccicheck warnings: ./drivers/soc/rockchip/io-domain.c:118:2-3: Unneeded semicolon. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/1629361749-97977-1-git-send-email-jiapeng.chong@linux.alibaba.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: io-domain: add rk3568 supportJianqun Xu2021-08-141-8/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The io-domain registers on RK3568 SoCs have three separated bits to enable/disable the 1.8v/2.5v/3.3v power. This patch make the write to be a operation, allow rk3568 uses a private register set function. Since the 2.5v mode hasn't been fully validated yet, the driver only sets 1.8v [enable] + 3.3v [disable] for 1.8v mode 1.8v [disable] + 3.3v [enable] for 3.3v mode There is not register order requirement which has been cleared by our IC team. For future reference the full usage matrix including the 2.5V setting is: case V33 V25 V18 result 0 0 0 0 IO safe, but cannot work 1 0 0 1 IO require 1.8V, should < 1.98V, otherwise IO may damage 2 0 1 0 IO require 2.5V, should < 2.75V, otherwise IO may damage 3 0 1 1 Invalid state, should avoid 4 1 0 0 IO require 3.3V, should < 3.63V, otherwise IO may damage 5 1 0 1 IO require 1.8V, should < 1.98V, otherwise IO may damage 6 1 1 0 IO require 2.5V, should < 2.75V, otherwise IO may damage 7 1 1 1 Invalid state, should avoid Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Tested-by: Peter Geis <pgwipeout@gmail.com> [added mode clarification from Jay] Link: https://lore.kernel.org/r/20210805120107.27007-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: ROCKCHIP_GRF should not default to y, unconditionallyGeert Uytterhoeven2021-07-121-2/+2
| | | | | | | | | | | Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ROCKCHIP_GRF to ARCH_ROCKCHIP, and ask the user in case of compile-testing. Fixes: 4c58063d4258f6be ("soc: rockchip: add driver handling grf setup") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210208143855.418374-1-geert+renesas@glider.be Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: add rk3568 powerdomainsElaine Zhang2021-05-111-0/+31
| | | | | | | | | Add power-domains found on rk3568 socs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210417112952.8516-16-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: Add a meaningful power domain nameElaine Zhang2021-05-101-107/+114
| | | | | | | | | | Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210417112952.8516-10-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe()Zhang Changzhong2020-12-041-0/+1
| | | | | | | | | | | Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: e943c43b32ce ("PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com> Link: https://lore.kernel.org/r/1607070805-33038-1-git-send-email-zhangchangzhong@huawei.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: io-domain: Remove incorrect and incomplete comment headerLee Jones2020-11-121-3/+0
| | | | | | | | | | | | | | | | Fixes the following W=1 kernel build warning(s): drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand * @supplies: voltage settings matching the register bits. Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com> Cc: Doug Anderson <dianders@chromium.org> Cc: linux-rockchip@lists.infradead.org Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* PM: AVS: rockchip-io: Move the driver to the rockchip specific driversUlf Hansson2020-10-163-0/+639
| | | | | | | | | | | | | | The avs drivers are all SoC specific drivers that doesn't share any code. Instead they are located in a directory, mostly to keep similar functionality together. From a maintenance point of view, it makes better sense to collect SoC specific drivers like these, into the SoC specific directories. Therefore, let's move the rockchip-io driver to the rockchip directory. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2019-07-201-115/+115
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: - A driver for SCU (system control) on NXP i.MX8QXP - Qualcomm Always-on Subsystem messaging driver (AOSS QMP) - Qualcomm PM support for MSM8998 - Support for a newer version of DRAM PHY driver for Broadcom (DPFE) - Reset controller support for Bitmain BM1880 - TI SCI (System Control Interface) support for CPU control on AM654 processors - More TI sysc refactoring and rework" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits) reset: remove redundant null check on pointer dev soc: rockchip: work around clang warning dt-bindings: reset: imx7: Fix the spelling of 'indices' soc: imx: Add i.MX8MN SoC driver support soc: aspeed: lpc-ctrl: Fix probe error handling soc: qcom: geni: Add support for ACPI firmware: ti_sci: Fix gcc unused-but-set-variable warning firmware: ti_sci: Use the correct style for SPDX License Identifier soc: imx8: Use existing of_root directly soc: imx8: Fix potential kernel dump in error path firmware/psci: psci_checker: Park kthreads before stopping them memory: move jedec_ddr.h from include/memory to drivers/memory/ memory: move jedec_ddr_data.c from lib/ to drivers/memory/ MAINTAINERS: Remove myself as qcom maintainer soc: aspeed: lpc-ctrl: make parameter optional soc: qcom: apr: Don't use reg for domain id soc: qcom: fix QCOM_AOSS_QMP dependency and build errors memory: tegra: Fix -Wunused-const-variable firmware: tegra: Early resume BPMP soc/tegra: Select pinctrl for Tegra194 ...
| * soc: rockchip: work around clang warningArnd Bergmann2019-07-041-115/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang emits a warning about a negative shift count for an unused part of a conditional constant expression: drivers/soc/rockchip/pm_domains.c:795:21: error: shift count is negative [-Werror,-Wshift-count-negative] [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/soc/rockchip/pm_domains.c:129:2: note: expanded from macro 'DOMAIN_RK3328' DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/soc/rockchip/pm_domains.c:105:33: note: expanded from macro 'DOMAIN_M' .status_mask = (status >= 0) ? BIT(status) : 0, \ ^~~~~~~~~~~ include/linux/bits.h:6:24: note: expanded from macro 'BIT' This is a bug in clang that will be fixed in the future, but in order to build cleanly with clang-8, it would be helpful to shut up this warning. This file is the only instance reported by kernelci at the moment. The best solution I could come up with is to move the BIT() usage out of the macro into the instantiation, so we can avoid using BIT(-1). Link: https://lore.kernel.org/r/20190703153112.2767411-1-arnd@arndb.de Link: https://bugs.llvm.org/show_bug.cgi?id=38789 Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-192-8/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
| | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* soc: rockchip: Set the proper PWM for rk3288Douglas Anderson2019-04-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The rk3288 SoC has two PWM implementations available, the "old" implementation and the "new" one. You can switch between the two of them by flipping a bit in the grf. The "old" implementation is the default at chip power up but isn't the one that's officially supposed to be used. ...and, in fact, the driver that gets selected in Linux using the rk3288 device tree only supports the "new" implementation. Long ago I tried to get a switch to the right IP block landed in the PWM driver (search for "rk3288: Switch to use the proper PWM IP") but that got rejected. In the mean time the grf has grown a full-fledged driver that already sets other random bits like this. That means we can now get the fix landed. For those wondering how things could have possibly worked for the last 4.5 years, folks have mostly been relying on the bootloader to set this bit. ...but occasionally folks have pointed back to my old patch series [1] in downstream kernels. [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: add rk3066 powerdomainsHeiko Stuebner2018-11-061-0/+24
| | | | | | Add power-domains found on rk3066 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: add rk3188 powerdomainsHeiko Stuebner2018-11-051-0/+24
| | | | | | Add power-domains found on rk3188 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: Convert to using %pOFn instead of device_node.nameRob Herring2018-10-041-22/+22
| | | | | | | | | | | | | | | | | | In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Li Yang <leoyang.li@nxp.com> Cc: David Brown <david.brown@linaro.org> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-soc@vger.kernel.org Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Qiang Zhao <qiang.zhao@nxp.com> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2018-06-121-1/+116
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "This contains platform-related driver updates for ARM and ARM64. Highlights: - ARM SCMI (System Control & Management Interface) driver cleanups - Hisilicon support for LPC bus w/ ACPI - Reset driver updates for several platforms: Uniphier, - Rockchip power domain bindings and hardware descriptions for several SoCs. - Tegra memory controller reset improvements" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (59 commits) ARM: tegra: fix compile-testing PCI host driver soc: rockchip: power-domain: add power domain support for px30 dt-bindings: power: add binding for px30 power domains dt-bindings: power: add PX30 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3228 dt-bindings: power: add binding for rk3228 power domains dt-bindings: power: add RK3228 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3128 dt-bindings: power: add binding for rk3128 power domains dt-bindings: power: add RK3128 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3036 dt-bindings: power: add binding for rk3036 power domains dt-bindings: power: add RK3036 SoCs header for power-domain dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Register SMMU after MC driver became ready soc: mediatek: remove unneeded semicolon soc: mediatek: add a fixed wait for SRAM stable soc: mediatek: introduce a CAPS flag for scp_domain_data soc: mediatek: reuse regmap_read_poll_timeout helpers ...
| * soc: rockchip: power-domain: add power domain support for px30Finley Xiao2018-05-231-0/+30
| | | | | | | | | | | | | | | | | | This driver is modified to support PX30 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: power-domain: add power domain support for rk3228Elaine Zhang2018-05-231-0/+28
| | | | | | | | | | | | | | | | This driver is modified to support RK3228 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: power-domain: add power domain support for rk3128Elaine Zhang2018-05-231-0/+24
| | | | | | | | | | | | | | | | This driver is modified to support RK3128 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: power-domain: add power domain support for rk3036Caesar Wang2018-05-231-0/+33
| | | | | | | | | | | | | | | | | | This driver is modified to support RK3036 SoC. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * soc: rockchip: power-domain: Fix wrong value when power up pd with writemaskFinley Xiao2018-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Solve the pd could only ever turn off but never turn them on again, if the pd registers have the writemask bits. So far this affects the rk3328 only. Fixes: 79bb17ce8edb ("soc: rockchip: power-domain: Support domain control in hiword-registers") Cc: stable@vger.kernel.org Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2018-06-091-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
| * | soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open ↵Geert Uytterhoeven2018-05-021-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | coding As of_clk_get_parent_count() returns zero on failure, while of_count_phandle_with_args() might return a negative error code, this also fixes the issue of possibly using a negative number in the allocation below. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / treewide: Use struct_size() for devm_kmalloc() and friendsKees Cook2018-06-061-2/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaces open-coded struct size calculations with struct_size() for devm_*, f2fs_*, and sock_* allocations. Automatically generated (and manually adjusted) from the following Coccinelle script: // Direct reference to struct field. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL); @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // Same pattern, but can't trivially locate the trailing element name, // or variable name. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; expression SOMETHING, COUNT, ELEMENT; @@ - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP) + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP) Signed-off-by: Kees Cook <keescook@chromium.org>
* soc: rockchip: power-domain: Add a sanity check on pd->num_clksJeffy Chen2018-03-051-5/+10
| | | | | | | | | | | | | The of_count_phandle_with_args() can fail and return error(for example, rk3399 pd_vio doesn't have clocks). That would break the pd probe. Add a sanity check on pd->num_clks to avoid that. Fixes: 65084121d59d ("soc: rockchip: power-domain: use clk_bulk APIs") Reported-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: use clk_bulk APIsJeffy Chen2018-03-051-48/+42
| | | | | | | Use clk_bulk APIs, and also add error handling for clk enable. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: disable jtag switching for RK3128 SoCsXiao Yao2018-03-051-0/+14
| | | | | | | | | Disable IO function switching between sdmmc and jtag for RK3128 SoCs. Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: disable jtag switching for RK3228/RK3229 SoCsShawn Lin2018-02-121-0/+14
| | | | | | | | Disable IO function switching between sdmmc and jtag for RK3228 and RK3229 SoCs. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: power-domain: Use GENPD_FLAG_ACTIVE_WAKEUPGeert Uytterhoeven2017-11-081-12/+2
| | | | | | | | | | Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to remove the driver's own flag-based callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* soc: rockchip: power-domain: add power domain support for rk3366Elaine Zhang2017-07-201-0/+32
| | | | | | | This driver is modified to support RK3366 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: disable jtag switching for RK3328 SocShawn Lin2017-07-161-0/+14
| | | | | | | | Disable IO function switching between sdmmc and jtag for RK3328 Soc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* soc: rockchip: add driver handling grf setupHeiko Stuebner2017-01-063-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The General Register Files are an area of registers containing a lot of single-bit settings for numerous components as well full components like usbphy control. Therefore all used components are accessed via the syscon provided by the grf nodes or from the sub-devices created through the simple-mfd created from the grf node. Some settings are not used by anything but will need to be set up according to expectations on the kernel side. Best example is the force_jtag setting, which defaults to on and results in the soc switching the pin-outputs between jtag and sdmmc automatically depending on the card-detect status. This conflicts heavily with how the dw_mmc driver expects to do its work and also with the clock-controller, which has most likely deactivated the jtag clock due to it being unused. So far the handling of this setting was living in the mach-rockchip code for the arm32-based rk3288 but that of course doesn't work for arm64 socs and would also look ugly for further arm32 socs. Also always disabling this setting is quite specific to linux and its subsystems, other operating systems might prefer other settings, so that the bootloader cannot really set a sane default for all. So introduce a top-level driver for the grf that handles these settings that need to be a certain way but nobody cares about. Other needed settings might surface in the future and can then be added here, but only as a last option. Ideally general GRF settings should be handled in the driver needing them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* soc: rockchip: power-domain: add power domain support for rk3328Elaine Zhang2017-01-051-0/+29
| | | | | | | | The rk3328 uses the newly introduced support for power-domain control in hiword-mask registers. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 08:02:19 +0100