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* soc: qcom: smd-rpm: Correct size of outgoing messageBjorn Andersson2015-10-311-1/+1
| | | | | | | | | | | | With the removal of VLAIS the size was incorrectly changed to only cover the headers of the packet, resulting in "empty" requests being sent to the RPM. Correct this so the entire message is transfered. Fixes: 50e1b29b4438 ("soc: qcom: smd: Remove use of VLAIS") Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'v4.4-rockchip-drivers2' of ↵Olof Johansson2015-10-232-2/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Some fixes for the new power-domain driver, including restricting Rockchip Kconfig options, fixing a possible null-pointer and a typo in the dt-bindings. * tag 'v4.4-rockchip-drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: Correct paths in Rockchip power domains binding document soc: rockchip: power-domain: don't try to print the clock name in error case soc: rockchip: Restrict to ARCH_ROCKCHIP Signed-off-by: Olof Johansson <olof@lixom.net>
| * soc: rockchip: power-domain: don't try to print the clock name in error caseHeiko Stuebner2015-10-161-2/+2
| | | | | | | | | | | | | | | | | | When we never got the the clock-reference, i.e. when IS_ERR(clk) is true, don't try to print the clock name via %pC as this of course produces a null-pointer-dereference in __clk_get_name(). Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Caesar Wang <wxt@rock-chips.com>
| * soc: rockchip: Restrict to ARCH_ROCKCHIPThierry Reding2015-10-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | By definition this directory contains drivers that are specific to the Rockchip architecture. All Kconfig options should therefore depend on ARCH_ROCKCHIP to avoid exposing these symbols on other architectures. For example, this options currently shows up as new when doing an incremental build on PowerPC. Signed-off-by: Thierry Reding <treding@nvidia.com> [add COMPILE_TEST alternative condition] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | soc: qcom/smem: add HWSPINLOCK dependencyArnd Bergmann2015-10-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a build error when smem is enabled without hwspinlock: drivers/built-in.o: In function `qcom_smem_alloc': rockchip-efuse.c:(.text+0x7a3e4): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7a568): undefined reference to `__hwspin_unlock' drivers/built-in.o: In function `qcom_smem_remove': rockchip-efuse.c:(.text+0x7a5cc): undefined reference to `hwspin_lock_free' drivers/built-in.o: In function `qcom_smem_probe': rockchip-efuse.c:(.text+0x7a960): undefined reference to `hwspin_lock_request_specific' rockchip-efuse.c:(.text+0x7a988): undefined reference to `of_hwspin_lock_get_id' drivers/built-in.o: In function `qcom_smem_get': rockchip-efuse.c:(.text+0x7aa24): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7aafc): undefined reference to `__hwspin_unlock' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | Merge tag 'qcom-soc-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm ↵Arnd Bergmann2015-10-154-325/+423
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers Pull "Qualcomm ARM Based SoC Updates for 4.4" from Andy Gross: * Implement id_table driver matching in SMD * Avoid NULL pointer exception on remove of SMEM * Reorder SMEM/SMD configs * Make qcom_smem_get() return a pointer * Handle big endian CPUs correctly in SMEM * Represent SMD channel layout in structures * Use __iowrite32_copy() in SMD * Remove use of VLAIs in SMD * Handle big endian CPUs correctly in SMD/RPM * Handle big endian CPUs corretly in SMD * Reject sending SMD packets that are too large * Fix endianness issue in SCM __qcom_scm_is_call_available * Add missing prototype for qcom_scm_is_available() * Correct SMEM items for upper channels * Use architecture level to build SCM correctly * Delete unneeded of_node_put in SMD * Correct active/slep state flagging in SMD/RPM * Move RPM message ram out of SMEM DT node * tag 'qcom-soc-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm: soc: qcom: smem: Move RPM message ram out of smem DT node soc: qcom: smd-rpm: Correct the active vs sleep state flagging soc: qcom: smd: delete unneeded of_node_put firmware: qcom-scm: build for correct architecture level soc: qcom: smd: Correct SMEM items for upper channels qcom-scm: add missing prototype for qcom_scm_is_available() qcom-scm: fix endianess issue in __qcom_scm_is_call_available soc: qcom: smd: Reject send of too big packets soc: qcom: smd: Handle big endian CPUs soc: qcom: smd_rpm: Handle big endian CPUs soc: qcom: smd: Remove use of VLAIS soc: qcom: smd: Use __iowrite32_copy() instead of open-coding it soc: qcom: smd: Represent channel layout in structures soc: qcom: smem: Handle big endian CPUs soc: qcom: Make qcom_smem_get() return a pointer soc: qcom: Reorder SMEM/SMD configs soc: qcom: smem: Avoid NULL pointer exception on remove soc: qcom: smd: Implement id_table driver matching
| * | soc: qcom: smem: Move RPM message ram out of smem DT nodeStephen Boyd2015-10-141-43/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMEM is a software construct built on top of a DDR reserved region and sometimes a device memory region called RPM message ram. Having the RPM message ram in the smem DT node's reg property leads to the smem node being located in different places depending on if the message ram is being used or not. Let's add a qcom specific property, qcom,rpm-msg-ram, and point to the device memory from the SMEM node via a phandle. As SMEM is a software construct, it really needs to reside at the root of the DT regardless of whether it's using the message ram or not. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd-rpm: Correct the active vs sleep state flaggingBjorn Andersson2015-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BIT() was incorrectly inherited from family A and should not be used on family B where the state is denoted by an enum. Reported-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: delete unneeded of_node_putJulia Lawall2015-10-141-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device node iterators perform an of_node_put on each iteration, so putting an of_node_put before a continue results in a double put. A simplified version of the semantic match that finds this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; iterator i; @@ i(..., child, ...) { ... when != of_node_get(child) * of_node_put(child); ... * continue; } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Correct SMEM items for upper channelsBjorn Andersson2015-10-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update the SMEM items for the second set of SMD channels, as these where incorrect. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Reject send of too big packetsBjorn Andersson2015-10-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attempting to find room for a packet that's bigger than the fifo will never succeed and the calling process will be sleeping forever in the loop, waiting for enough room. So fail early instead. Reported-by: Courtney Cavin <courtney.cavin@sonymobile.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Handle big endian CPUsStephen Boyd2015-10-141-65/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smd structures are always in little endian, but the smd driver is not capable of being used on big endian CPUs. Annotate the little endian data members and update the code to do the proper byte swapping. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd_rpm: Handle big endian CPUsStephen Boyd2015-10-141-24/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smd rpm structures are always in little endian, but this driver is not capable of being used on big endian CPUs. Annotate the little endian data members and update the code to do the proper byte swapping. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Remove use of VLAISStephen Boyd2015-10-141-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usage of VLAIS prevents clang from compiling this file, and it also opens us to the possibility of allocating a large structure on the stack to the point that we blow past the limit of the kernel stack. Remove the VLAIS and allocate a structure on the heap with kmalloc so that we're safer and more clang friendly. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Use __iowrite32_copy() instead of open-coding itStephen Boyd2015-10-141-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | We already have a function to do this and it silences some sparse warnings along the way. Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Represent channel layout in structuresStephen Boyd2015-10-141-28/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rx and tx channel info are laid out in memory next to each other, and there are two types of channel info structures, byte based and word based. We have 4 pointers to these info structures, when we really only need two to point to the different types of structures. Encapsulate the byte based and word based tx/rx structures in a "channel pair" structure that describes the layout of memory and reduces the number of pointers in the smd channel structure by two. Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smem: Handle big endian CPUsStephen Boyd2015-10-141-91/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The contents of smem are always in little endian, but the smem driver is not capable of being used on big endian CPUs. Annotate the little endian data members and update the code to do the proper byte swapping. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: Make qcom_smem_get() return a pointerStephen Boyd2015-10-142-55/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Passing a void ** almost always requires a cast at the call site. Instead of littering the code with casts every time this function is called, have qcom_smem_get() return a void pointer to the location of the smem item. This frees the caller from having to cast the pointer. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: Reorder SMEM/SMD configsStephen Boyd2015-10-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I make nconfig, having the SMEM option after the SMD option causes the configurator to get confused when I'm enabling and disabling these options. Let's move SMEM before SMD so there's a clear indented dependency chain. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smem: Avoid NULL pointer exception on removeStephen Boyd2015-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't set a pointer to NULL and then dereference it in the next line. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * | soc: qcom: smd: Implement id_table driver matchingBjorn Andersson2015-10-141-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a id_table based driver maching mechanism for drivers that binds to fixed channels and doesn't need any additional configuration, e.g. IPCRTR and DIAG. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* | | Merge tag 'v4.4-rockchip-drivers1' of ↵Arnd Bergmann2015-10-095-0/+510
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Merge "Rockchip power-domain drivers for 4.4" from Heiko Stuebner: Add the power-domain base-driver which currently contains support for the rk3288 powerdomain layout but can be easily extended for the socs (including arm64) later on. A big thanks to Ceasar Wang for pulling through on this during 18 revisions. Also included is a fix to the pm-clock handling in the generic powerdomains to adapt it to the per-user clock handling we now do, Acked by Rafael Wysocki. * tag 'v4.4-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: Add power domain driver dt-bindings: add document of Rockchip power domains PM / clk: Do not __clk_get passed in clock-references dt-bindings: add power-domain header for RK3288 SoCs
| * | soc: rockchip: power-domain: Add power domain driverCaesar Wang2015-10-065-0/+510
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is found on RK3288 SoCs. In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power of the whole chip. PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON register. After setting the register, PMU would enter the Low Power mode. In the low power mode, pmu will auto power on/off the specified power domain, send idle req to specified power domain, shut down/up pll and so on. All of above are configurable by setting corresponding registers. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> [replace dsb() with dsb(sy) for arm64 buildability; sy is the default, so no functional change; adapt to per-user clocks in genpd] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | genirq: Remove irq argument from irq flow handlersThomas Gleixner2015-09-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
* | soc: dove: Prepare irq handler for irq argument removalThomas Gleixner2015-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | soc: dove: Use irq_desc_get_xxx() to avoid redundant lookup of irq_descThomas Gleixner2015-09-141-1/+1
|/ | | | | | | | Search and replace done with coccinelle Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
* Merge tag 'armsoc-late' of ↵Linus Torvalds2015-09-112-19/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull late ARM SoC updates from Kevin Hilman: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The bulk of the changes are for samsung/exynos SoCs for some changes that needed a few minor reworks so ended up a bit late. The others are mainly for qcom SoCs: a couple fixes and some DTS updates" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) ARM: multi_v7_defconfig: Enable PBIAS regulator soc: qcom: smd: Correct fBLOCKREADINTR handling soc: qcom: smd: Use correct remote processor ID soc: qcom: smem: Fix errant private access ARM: dts: qcom: msm8974-sony-xperia-honami: Use stdout-path ARM: dts: qcom: msm8960-cdp: Use stdout-path ARM: dts: qcom: msm8660-surf: Use stdout-path ARM: dts: qcom: ipq8064-ap148: Use stdout-path ARM: dts: qcom: apq8084-mtp: Use stdout-path ARM: dts: qcom: apq8084-ifc6540: Use stdout-path ARM: dts: qcom: apq8074-dragonboard: Use stdout-path ARM: dts: qcom: apq8064-ifc6410: Use stdout-path ARM: dts: qcom: apq8064-cm-qs600: Use stdout-path ARM: dts: qcom: Label serial nodes for aliasing and stdout-path reset: ath79: Fix missing spin_lock_init reset: Add (devm_)reset_control_get stub functions ARM: EXYNOS: switch to using generic cpufreq driver for exynos4x12 cpufreq: exynos: Remove unselectable rule for arm-exynos-cpufreq.o ARM: dts: add iommu property to JPEG device for exynos4 ARM: dts: enable SPI1 for exynos4412-odroidu3 ...
| * soc: qcom: smd: Correct fBLOCKREADINTR handlingBjorn Andersson2015-09-091-3/+3
| | | | | | | | | | | | | | | | | | | | fBLOCKREADINTR is masking the notification from the remote and should hence be cleared while we're waiting the tx fifo to drain. Also change the reset state to mask the notification, as send is the only use case where we're interested in it. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| * soc: qcom: smd: Use correct remote processor IDAndy Gross2015-09-091-4/+12
| | | | | | | | | | | | | | | | This patch fixes SMEM addressing issues when remote processors need to use secure SMEM partitions. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
| * soc: qcom: smem: Fix errant private accessAndy Gross2015-09-091-12/+6
| | | | | | | | | | | | | | | | This patch corrects private partition item access. Instead of falling back to global for instances where we have an actual host and remote partition existing, return the results of the private lookup. Signed-off-by: Andy Gross <agross@codeaurora.org>
* | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2015-09-0122-448/+3616
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
| * \ Merge tag 'tegra-for-4.3-soc' of ↵Olof Johansson2015-08-2114-448/+830
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers ARM: tegra: Core SoC changes for v4.3-rc1 This contains a bit more of Tegra210 support, which is shaping up pretty nicely. Other than that there are a couple of cleanup patches here, too. * tag 'tegra-for-4.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile soc/tegra: fuse: Add spare bit offset for Tegra210 soc/tegra: fuse: Add spare bit offset for Tegra124 soc/tegra: fuse: Add spare bit offset for Tegra114 soc/tegra: fuse: Rename core_* to soc_* soc/tegra: fuse: Add Tegra210 support soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers soc/tegra: fuse: Restrict legacy code to 32-bit ARM soc/tegra: pmc: Add Tegra210 support soc/tegra: pmc: Restrict legacy code to 32-bit ARM soc/tegra: pmc: Avoid usage of uninitialized variable soc/tegra: Add Tegra210 support soc/tegra: Add Tegra132 support Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | soc/tegra: pmc: Use existing pclk referenceThierry Reding2015-08-131-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver requests the pclk clock at probe time already and stores its reference to it in struct tegra_pmc, so there is no need to look it up everytime it is needed. Use the existing reference instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: pmc: Remove unnecessary return statementThierry Reding2015-08-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Functions returning no value don't need an explicit return statement. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in MakefileMasahiro Yamada2015-08-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kbuild descends into drivers/soc/tegra/ only when CONFIG_ARCH_TEGRA is enabled. (see drivers/soc/Makefile) $(CONFIG_ARCH_TEGRA) in drivers/soc/tegra/Makefile always evaluates to 'y'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Add spare bit offset for Tegra210Thierry Reding2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset of the first spare bit register on Tegra210 is 0x380, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Add spare bit offset for Tegra124Thierry Reding2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset of the first spare bit register on Tegra124 is 0x300, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Add spare bit offset for Tegra114Thierry Reding2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset of the first spare bit register on Tegra114 is 0x280, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Rename core_* to soc_*Thierry Reding2015-07-167-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a mixture of core_* and soc_* prefixes for variables storing information related to the VDD_CORE rail. Choose one (soc_*) and use it more consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Add Tegra210 supportThierry Reding2015-07-165-1/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Unify Tegra20 and Tegra30 driversThierry Reding2015-07-1610-367/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: fuse: Restrict legacy code to 32-bit ARMThierry Reding2015-07-161-9/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For backwards-compatibility with old device trees, if no APBMISC node exists this driver hard-codes the I/O memory region. All 64-bit ARM device tree files are recent enough that they can be required to have this node, and therefore the legacy code path is not required. Based on work done by Paul Walmsley <pwalmsley@nvidia.com>. Cc: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: pmc: Add Tegra210 supportThierry Reding2015-07-161-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 uses a power management controller that is compatible with earlier SoC generations but adds a couple of power partitions for new hardware blocks. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: pmc: Restrict legacy code to 32-bit ARMThierry Reding2015-07-161-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For backwards-compatibility with old device trees, if no PMC node exists this driver hard-codes the I/O memory region. All 64-bit ARM device tree files are recent enough that they can be required to have this node, and therefore the legacy code path is not required on 64-bit ARM. Based on work done by Paul Walmsley <pwalmsley@nvidia.com>. Cc: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: pmc: Avoid usage of uninitialized variableThierry Reding2015-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure to only drop the reference to the OF node after it's been successfully obtained. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: <stable@vger.kernel.org> # v4.0+ Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: Add Tegra210 supportThierry Reding2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add Tegra210 to the matching table for NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | soc/tegra: Add Tegra132 supportThierry Reding2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add Tegra132 to the matching table for NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | Merge tag 'qcom-soc-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm ↵Olof Johansson2015-08-135-0/+2372
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers Qualcomm ARM Based SoC Updates for 4.3 * Add SMEM driver * Add SMD driver * Add RPM over SMD driver * Select QCOM_SCM by default * tag 'qcom-soc-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm: devicetree: soc: Add Qualcomm SMD based RPM DT binding soc: qcom: Driver for the Qualcomm RPM over SMD soc: qcom: Add Shared Memory Driver soc: qcom: Add device tree binding for Shared Memory Device drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PM soc: qcom: Add Shared Memory Manager driver Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | soc: qcom: Driver for the Qualcomm RPM over SMDBjorn Andersson2015-07-293-0/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
| | * | soc: qcom: Add Shared Memory DriverBjorn Andersson2015-07-293-0/+1328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the Qualcomm Shared Memory Driver (SMD) providing communication channels to remote processors, ontop of SMEM. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-08 20:38:22 +0100