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path: root/drivers/spi/spi-dw.h (follow)
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* spi: dw-mid: constify dw_spi_dma_ops structureJulia Lawall2015-11-301-1/+1
| | | | | | | | | | The dw_spi_dma_ops structure is never modified, so declare it as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: introduce spi_shutdown_chip()Andy Shevchenko2015-10-191-0/+6
| | | | | | | This helper disables SPI controller and sets clock to 0. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Allow interface drivers to limit data I/O to word sizesMichael van der Westhuizen2015-08-211-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Both the core and the MMIO interface driver default to the current 32bit behaviour. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-spi: Convert 16bit accesses to 32bit accessesThor Thayer2015-03-171-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Altera's Arria10 SoC interconnect requires a 32-bit write for APB peripherals. The current spi-dw driver uses 16-bit accesses in some locations. This patch converts all the 16-bit reads and writes to 32-bit reads and writes. Additional Documentation to Support this Change: The DW_apb_ssi databook states: "All registers in the DW_apb_ssi are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from these bits returns 0." [1] [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Request for test with platforms using the DesignWare SPI IP. Tested On: Altera CycloneV development kit Altera Arria10 development kit Compile tested for build errors on x86_64 (allyesconfigs) Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Reviewed-and-tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: convert to use dw_dmac instead of intel_mid_dmaAndy Shevchenko2015-03-091-2/+2
| | | | | | | | | intel_mid_dma seems to be unmaintained for a long time. Moreover, the IP block of DMA itself is the same in both dw_dmac and intel_mid_dma. This patch moves spi-dw-midpci to use dw_dmac driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: move to use core SPI DMA mappingsAndy Shevchenko2015-03-091-11/+6
| | | | | | | | SPI core has a comprehensive function set to map and unmap a message when it's needed. This patch converts driver to use that advantage. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: clear ongoing DMA transfers on timeoutAndy Shevchenko2015-03-091-0/+1
| | | | | | | This patch shuts up any ongoing DMA transfer in case of error. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: split dma_setup() from dma_transfer()Andy Shevchenko2015-03-091-2/+2
| | | | | | | | | | | The patch splits DMA preparatory code to dma_setup() callback. The change also converts transfer_one() to program DMA whenever the transfer is DMA mapped. The change is a follow up of the converion to use SPI core transfer_one_message(). Since the DMA mapped transfers can be interleaved with PIO ones the DMA related configuration should respect that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: move to SPI core message handlingAndy Shevchenko2015-03-061-26/+0
| | | | | | | | This patch removes a lot of duplicate code since SPI core provides a nice message handling. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: make sure SPI controller is enabledAndy Shevchenko2015-03-061-0/+12
| | | | | | | | | | | | | | | | The error handling is partially broken since the controller is disabled on error and is not re-enabled until condition occurs, i.e. mode (poll, PIO/DMA), chip (cs_change), or speed (clk_div) is changed. In the result of these changes we will have a predictable state of the SPi controller independently on how successfull was a previous transfer. The patch disables interrupts and re-enables the SPI controller wherever it needs to be done. Thus most of the time the SPI controller is kept enabled. The runtime PM, when it will be implemented, must take care of the controller disabling and re-enabling. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: split rx and tx callbacks when DMAAndy Shevchenko2014-10-281-1/+1
| | | | | | | | | Currently driver wouldn't work properly if user asked for simplex transfer. The patch separates DMA rx and tx callbacks and finishes transfer correctly in any case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: change magic numbers to the constantsAndy Shevchenko2014-10-021-0/+4
| | | | | | | | | | Instead of using magic numbers in the code we create a bit map definition of the DMACR register and use it. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw-mid: remove redundant dmac memberAndy Shevchenko2014-09-131-1/+0
| | | | | | | | Instead of using that member we prefer to use dma_dev which represents actual struct device of the DMA device. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: remove FSF addressAndy Shevchenko2014-09-131-3/+3
| | | | | | | | | | There is no need to keep FSF address in the head of the file. While here, fix few typos in the header. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: add support for gpio controlled chip selectBaruch Siach2014-04-241-5/+11
| | | | | | | | Also, use this opportunity to let spi_chip_sel() handle chip-select deactivation as well. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
* spi: dw: migrate to generic queue infrastructureBaruch Siach2014-04-241-8/+0
| | | | | Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
* spi: dw: use managed resourcesBaruch Siach2013-12-311-3/+1
| | | | | | | | | Migrate mmio code and core driver to managed resources to reduce boilerplate error handling code. Also, handle clk_enable() failure while at it, and drop unused dw_spi iolen field. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
* spi: dw: drop unused struct dw_spi fieldBaruch Siach2013-12-301-1/+0
| | | | | Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
* spi: spi-dw: fix all sparse warningsH Hartley Sweeten2011-09-211-44/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_{read,write}[lw] macros produce sparse warnings everytime they are used. The "read" ones cause: warning: cast removes address space of expression warning: incorrect type in argument 1 (different address spaces) expected void const volatile [noderef] <asn:2>*addr got unsigned int *<noident> And the "write" ones: warning: cast removes address space of expression warning: incorrect type in argument 2 (different address spaces) expected void volatile [noderef] <asn:2>*addr got unsigned int *<noident> Fix this by removing struct dw_spi_reg and converting all the register offsets to #defines. Then convert the macros into inlined functions so that proper type checking can occur. While here, also fix the three sparse warnings in spi-dw-mid.c due to the return value of ioremap_nocache being stored in a u32 * not a void __iomem *. With these changes the spi-dw* files all build with no sparse warnings. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* spi/dw: Add spi number into spi irq descLiu, ShuoX2011-07-081-0/+1
| | | | | Signed-off-by: ShuoX Liu <shuox.liu@intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* spi: reorganize driversGrant Likely2011-06-061-0/+232
Sort the SPI makefile and enforce the naming convention spi_*.c for spi drivers. This change also rolls the contents of atmel_spi.h into the .c file since there is only one user of that particular include file. v2: - Use 'spi-' prefix instead of 'spi_' to match what seems to be be the predominant pattern for subsystem prefixes. - Clean up filenames in Kconfig and header comment blocks Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>