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path: root/drivers/spi/spi-zynq-qspi.c (follow)
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* spi: zynq-qspi: Clarify the select chip functionMiquel Raynal2019-11-081-11/+6
| | | | | | | | | | | | | | The code used to assert and de-assert a chip select line is very complicated for no reason. Simplify the logic by either setting or resetting the concerned bit, which actually only changes an electrical state. Update the comment to reflect that there is no possibility to actually choose a CS as the default (CS0) will be driven in any case. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191108140744.1734-6-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: Enhance the Linear CFG bit definitionsMiquel Raynal2019-11-081-3/+3
| | | | | | | | | | | Using masks makes sense when manipulating fields of several bits. When only one bit is involved, it is usual to just use the BIT() macro but in this case using the term mask is abusive. Fix the #define macros and their comments. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191108140744.1734-5-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: Keep the bitfields naming consistentMiquel Raynal2019-11-081-6/+6
| | | | | | | | | | | | | Most of the bits/bitfields #define'd in this driver are composed with: 1/ the driver prefix 2/ the name of the register they apply to Keep the naming consistent by applying this rule to the CONFIG register internals. These definitions will be used in a following change set. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191108140744.1734-4-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: Anything else than CS0 is not supported yetMiquel Raynal2019-11-081-2/+6
| | | | | | | | | Unlike what the driver is currently advertizing, CS0 only can be used, CS1 is not supported at all. Prevent people to use CS1. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191108140744.1734-2-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: Keep the naming consistent across the driverMiquel Raynal2019-11-081-5/+5
| | | | | | | | | | | In this driver (and also in a lot of other drivers in drivers/spi/), the spi_controller structure is sometimes referred as 'ctlr' and sometimes as 'ctrl'. Grepping there shows that 'ctlr' seems to be more common so keep the naming consistent in this driver and s/ctrl/ctlr/. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191108105920.19014-3-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: Drop GPIO headerLinus Walleij2019-10-301-1/+0
| | | | | | | | | This driver does not use any symbols from the legacy GPIO header so drop the include. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191030073624.23974-1-linus.walleij@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynq-qspi: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-09-041-3/+1
| | | | | | | | | | Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190904135918.25352-36-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'spi-5.3' into spi-5.4Mark Brown2019-08-231-1/+1
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| * spi: zynq-qspi: Fix missing spi_unregister_controller when unload moduleAxel Lin2019-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | Use devm_spi_register_controller to fix missing spi_unregister_controller when unload module. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20190818095113.2397-1-axel.lin@ingics.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: Remove dev_err() usage after platform_get_irq()Stephen Boyd2019-08-021-1/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: zynq-qspi: Fix build error on architectures missing readsl/writeslNaga Sureshkumar Relli2019-05-021-4/+4
| | | | | | | | | | Alpha and some of the architectures are missing readsl/writesl functions. so the zynq-qspi driver won't be able to build on these arches. hence use ioread32_rep()/iowrite32_rep() instead of readsl()/writesl(). Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: Add support for Zynq QSPI controllerNaga Sureshkumar Relli2019-04-051-0/+761
Add support for QSPI controller driver used by Xilinx Zynq SOC. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>