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* spi: dw: Add Elkhart Lake PSE DMA supportJarkko Nikula2020-05-063-0/+46
| | | | | | | | | | | | | Elkhart Lake PSE SPI is capable to utilize PSE DMA engine which is described in ACPI. With help of acpi-dma module the support becomes a generic one. Thus, add Elkhart Lake PSE DMA support and generic DMA hooks in SPI DesignWare driver. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-8-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Propagate struct device pointer to ->dma_init() callbackAndy Shevchenko2020-05-063-3/+3
| | | | | | | | | | In some cases, one of which is coming soon, we would like to have a struct device pointer to request DMA channel. For this purpose propagate it to ->dma_init() callback in DMA ops. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-7-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add 'mfld' suffix to Intel Medfield related routinesAndy Shevchenko2020-05-063-13/+18
| | | | | | | | | | | | | | In order to prepare driver for the extension to support newer hardware, add 'mfld' suffix to some related functions. While here, move DMA parameters assignment under existing #ifdef CONFIG_SPI_DW_MID_DMA. There is no functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-6-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Move few headers under #ifdef CONFIG_SPI_DW_MID_DMAAndy Shevchenko2020-05-061-3/+2
| | | | | | | | | | | There is no user of few headers without CONFIG_SPI_DW_MID_DMA being set. Move them under condition. While at it, remove unused slab.h there. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-5-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Downgrade interrupt.h to irqreturn.h where appropriateAndy Shevchenko2020-05-062-2/+2
| | | | | | | | | | | | | spi-dw-mid.c along with spi-dw.h are direct users of irqreturn.h and nothing else is being used from interrupt.h. So, switch them to use the former instead of latter one. While here, move the header under #ifdef CONFIG_SPI_DW_MID_DMA in spi-dw-mid.c. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-4-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Move interrupt.h to spi-dw.h who is user of itAndy Shevchenko2020-05-063-2/+1
| | | | | | | | | The actual user of interrupt.h is spi-dw.h and not bus drivers. Move header there. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-3-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Remove unused variable in CR0 configuring hooksAndy Shevchenko2020-05-061-2/+0
| | | | | | | | | | | | | | | | | | | | After enabling new IP support in the driver couple of variables were left unused compiler is not happy about: .../spi-dw.c: In function ‘dw_spi_update_cr0’: .../spi-dw.c:264:17: warning: unused variable ‘dws’ [-Wunused-variable] 264 | struct dw_spi *dws = spi_controller_get_devdata(master); | ^~~ .../spi-dw.c: In function ‘dw_spi_update_cr0_v1_01a’: .../spi-dw.c:285:17: warning: unused variable ‘dws’ [-Wunused-variable] 285 | struct dw_spi *dws = spi_controller_get_devdata(master); | ^~~ Drop them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Zero DMA Tx and Rx configurations on stackAndy Shevchenko2020-05-061-0/+2
| | | | | | | | | | | | | | Some DMA controller drivers do not tolerate non-zero values in the DMA configuration structures. Zero them to avoid issues with such DMA controller drivers. Even despite above this is a good practice per se. Fixes: 7063c0d942a1 ("spi/dw_spi: add DMA support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Feng Tang <feng.tang@intel.com> Cc: Feng Tang <feng.tang@intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835: Fix error return code in bcm2835_dma_init()Wei Yongjun2020-05-061-0/+4
| | | | | | | | | Fix to return negative error code -ENOMEM from the dma mapping error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200506125607.90952-1-weiyongjun1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: a3700: make a3700_spi_init() return voidJason Yan2020-05-061-7/+3
| | | | | | | | | | | Fix the following coccicheck warning: drivers/spi/spi-armada-3700.c:283:8-11: Unneeded variable: "ret". Return "0" on line 315 Signed-off-by: Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200506061911.19923-1-yanaijie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add support for Intel Keem Bay SPIWan Ahmad Zainie2020-05-051-0/+26
| | | | | | | | | | | Add support for Intel Keem Bay SPI controller, which uses DesignWare DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to configure the device as a master or as a slave serial peripheral. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-6-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add support for DesignWare DWC_ssiWan Ahmad Zainie2020-05-053-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is the enhanced version of DW_apb_ssi, which is currently supported by this driver. Their registers are same, but the bit fields of register CTRLR0 are different. DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave device. Register offset DW_ssi DW_apb_ssi CTRLR0 0x00 0x00 CTRLR1 0x04 0x04 SSIENR 0x08 0x08 MWCR 0x0c 0x0c SER 0x10 0x10 BAUDR 0x14 0x14 TXFTLR 0x18 0x18 RXFTLR 0x1c 0x1c TXFLR 0x20 0x20 RXFLR 0x24 0x24 SR 0x28 0x28 IMR 0x2c 0x2c ISR 0x30 0x30 RISR 0x34 0x34 TXOICR 0x38 0x38 RXOICR 0x3c 0x3c RXUICR 0x40 0x40 MSTICR 0x44 0x44 ICR 0x48 0x48 DMACR 0x4c 0x4c DMATDLR 0x50 0x50 DMARDLR 0x54 0x54 IDR 0x58 0x58 SSI_VERSION_ID 0x5c 0x5c DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4 RX_SAMPLE_DLY 0xf0 0xf0 SPI_CTRLR0 0xf4 0xf4 TXD_DRIVE_EDGE 0xf8 0xf8 XIP_MODE_BITS 0xfc RSVD Register configuration - CTRLR0 DW_ssi DW_apb_ssi SPI_HYPERBUS_EN bit[24] NONE SPI_FRF bit[23:22] bit[22:21] DFS_32 NONE bit[20:16] CFS bit[19:16] bit[15:12] SSTE bit[14] bit[24] SRL bit[13] bit[11] SLV_OE bit[12] bit[10] TMOD bit[11:10] bit[9:8] SCPOL | SPHA bit[9:8] bit[7:6] FRF bit[7:6] bit[5:4] DFS bit[4:0] bit[3:0] The documents used are [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a). [2] DWC_ssi_databook.pdf version 1.01a. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add update_cr0() callback to update CTRLR0Wan Ahmad Zainie2020-05-054-11/+48
| | | | | | | | | | | | | This patch adds update_cr0() callback, in struct dw_spi. Existing code that configure register CTRLR0 is moved into a new function, dw_spi_update_cr0(), and this will be the default. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Fix typo in few registers nameWan Ahmad Zainie2020-05-052-13/+13
| | | | | | | | | | | | This patch will fix typo in the register name used in the source code, to be consistent with the register name used in the databook. Databook: DW_apb_ssi_databook.pdf version 4.01a Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835: Fixes bare use of unsignedJacko Dirks2020-05-051-2/+2
| | | | | | Signed-off-by: Jacko Dirks <jdirks.linuxdev@gmail.com> Link: https://lore.kernel.org/r/20200503200033.GA3256@vasteMachine Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge series "Grab bag with AMD SPI fixes" from Lukas Wunner <lukas@wunner.de>:Mark Brown2020-05-051-22/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here's an assortment of drive-by fixes for the new AMD SPI driver. All of them are compile-tested only. Lukas Wunner (5): spi: amd: Fix duplicate iounmap in error path spi: amd: Pass probe errors back to driver core spi: amd: Drop duplicate driver data assignments spi: amd: Fix refcount underflow on remove spi: amd: Drop superfluous member from struct amd_spi drivers/spi/spi-amd.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) -- 2.26.2
| * spi: amd: Drop superfluous member from struct amd_spiLukas Wunner2020-05-041-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | The AMD SPI driver stores a pointer to the spi_master in struct amd_spi so that it can get from the latter to the former in amd_spi_fifo_xfer(). It's simpler to just pass the pointer from the sole caller amd_spi_master_transfer() and drop the pointer from struct amd_spi. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/a088b684ad292faf3bd036e51529e608e5c94638.1588590210.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: amd: Fix refcount underflow on removeLukas Wunner2020-05-041-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMD SPI driver calls spi_master_put() in its ->remove() hook even though the preceding call to spi_unregister_master() already drops a ref, thus leading to a refcount underflow. Drop the superfluous call to spi_master_put(). This only leaves the call to spi_unregister_master() in the ->remove() hook, so it's safe to change the ->probe() hook to use the devm version of spi_register_master() and drop the ->remove() hook altogether. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/5e53ccdf1eecd4e015dba99d0d77389107f8a2e3.1588590210.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: amd: Drop duplicate driver data assignmentsLukas Wunner2020-05-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | The AMD SPI driver calls platform_set_drvdata() on probe even though it's already been set by __spi_alloc_controller(). Likewise, it calls platform_set_drvdata() on remove even though it's going to be set by __device_release_driver(). Drop the duplicate assignments. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/499f8ad4759c2ff0f586e0459fb9a293faecff6d.1588590210.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: amd: Pass probe errors back to driver coreLukas Wunner2020-05-041-1/+1
| | | | | | | | | | | | | | | | | | If probing fails, the AMD SPI driver pretends success to the driver core by returning 0. Return the errno instead. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/689f29a359718dab4f5de9ee66c02ea97b3bd9e8.1588590210.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: amd: Fix duplicate iounmap in error pathLukas Wunner2020-05-041-3/+1
| | | | | | | | | | | | | | | | | | | | | | The AMD SPI driver uses devm_ioremap_resource() to map its registers, so they're automatically unmapped via device_release() when the last ref on the SPI controller is dropped. The additional iounmap() in the ->probe() error path is thus unnecessary. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/497cc38ae2beb7900ae05a1463eb83ff96e2770e.1588590210.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
* | Merge branch 'for-5.7' of ↵Mark Brown2020-05-055-39/+47
|\ \ | |/ |/| | | https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.8
| * spi: bcm-qspi: Handle clock probe deferralFlorian Fainelli2020-04-211-7/+5
| | | | | | | | | | | | | | | | | | | | | | The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional(). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200420190853.45614-2-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: bcm-qspi: when tx/rx buffer is NULL set to 0Justin Chen2020-04-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we set the tx/rx buffer to 0xff when NULL. This causes problems with some spi slaves where 0xff is a valid command. Looking at other drivers, the tx/rx buffer is usually set to 0x00 when NULL. Following this convention solves the issue. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200420190853.45614-6-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: bcm-qspi: Make PM suspend/resume work with SCMI clock managementKamal Dasu2020-04-211-2/+2
| | | | | | | | | | | | | | | | | | | | SCMI only passes clk_prepare_enable() and clk_disable_unprepare(), made changes to suspend/resume ops to use the appropriate calls so that PM works for ARM and ARM64 platforms. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-7-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_changeKamal Dasu2020-04-211-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the spi core implementation for MSPI devices when the transfer is the last one in the message, the chip may stay selected until the next transfer. On multi-device SPI busses with nothing blocking messages going to other devices, this is just a performance hint; starting a message to another device deselects this one. But in other cases, this can be used to ensure correctness. Some devices need protocol transactions to be built from a series of spi_message submissions, where the content of one message is determined by the results of previous messages and where the whole transaction ends when the chipselect goes intactive. On CS change after completing the last serial transfer, the MSPI driver drives SSb pin CDRAM register correctly according comments in core spi.h as shown below: case 1) EOM =1, cs_change =0: SSb inactive case 2) EOM =1, cs_change =1: SSb active case 3) EOM =0, cs_change =0: SSb active case 4) EOM =0, cs_change =1: SSb inactive Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-5-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Respect DataBitLength field of SpiSerialBusV2() ACPI resourceAndy Shevchenko2020-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By unknown reason the commit 64bee4d28c9e ("spi / ACPI: add ACPI enumeration support") missed the DataBitLength property to encounter when parse SPI slave device data from ACPI. Fill the gap here. Fixes: 64bee4d28c9e ("spi / ACPI: add ACPI enumeration support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200413180406.1826-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: sc18is602: Fix a typo in MODULE_DESCRIPTIONChristophe JAILLET2020-04-141-1/+1
| | | | | | | | | | | | | | | | This should be 'SC18IS602', not 'SC18IC602' Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200413154043.23064-1-christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: spi-axi-spi-engine: Access register after clock initializationRafał Hibner2020-04-091-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | Move register access after clock initialization. Clock "s_axi_aclk" is needed for register access. Without the clock running AXI bus hangs and causes kernel freeze. Signed-off-by: Rafał Hibner <rafal.hibner@secom.com.pl> Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Cc: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20200409155621.12174-1-rafal.hibner@secom.com.pl Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: spi-ep93xx: fix wrong SPI mode selectionJungseung Lee2020-04-031-2/+6
| | | | | | | | | | | | | | | | | | | | The mode bits on control register 0 are in a different order compared to the spi mode define values. Thus, in the current code, it fails to set the correct SPI mode selection. Fix it. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Link: https://lore.kernel.org/r/20200402121022.9976-1-js07.lee@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: atmel: Add missing annotation for atmel_spi_next_xfer_dma_submit()Jules Irenge2020-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse reports a warning at atmel_spi_next_xfer_dma_submit() warning: context imbalance in atmel_spi_next_xfer_dma_submit() - unexpected unlock The root cause is the missing annotation at atmel_spi_next_xfer_dma_submit() Add the missing __must_hold(&as->lock) annotation Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Link: https://lore.kernel.org/r/20200429225723.31258-3-jbi.octave@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: pxa2xx: Apply CS clk quirk to BXTEvan Green2020-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a couple allies at Intel, and much badgering, I got confirmation from Intel that at least BXT suffers from the same SPI chip-select issue as Cannonlake (and beyond). The issue being that after going through runtime suspend/resume, toggling the chip-select line without also sending data does nothing. Add the quirk to BXT to briefly toggle dynamic clock gating off and on, forcing the fabric to wake up enough to notice the CS register change. Signed-off-by: Evan Green <evgreen@chromium.org> Cc: Shobhit Srivastava <shobhit.srivastava@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: stm32-qspi: Fix unbalanced pm_runtime_enable issuePatrice Chotard2020-04-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue detected by unbinding/binding the stm32 qspi driver as following: root@stm32mp2:~# echo 40430000.spi > /sys/bus/platform/drivers/stm32-qspi/404300 00.spi/driver/unbind root@stm32mp2:~# echo 40430000.spi > /sys/bus/platform/drivers/stm32-qspi/bind [ 969.864021] stm32-qspi 40430000.spi: Unbalanced pm_runtime_enable! [ 970.225161] spi-nor spi0.0: mx66u51235f (65536 Kbytes) [ 970.935721] spi-nor spi0.1: mx66u51235f (65536 Kbytes) Fixes: 9d282c17b023 ("spi: stm32-qspi: Add pm_runtime support") Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Link: https://lore.kernel.org/r/20200429102625.25974-1-patrice.chotard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: uniphier: fix error return code in uniphier_spi_probe()Wei Yongjun2020-04-291-2/+6
| | | | | | | | | | | | | | | | | | Fix to return negative error code -EPROBE_DEFER from the DMA probe defer error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200429075855.104487-1-weiyongjun1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-amd: Fix a NULL vs IS_ERR() check in amd_spi_probe()Wei Yongjun2020-04-291-3/+2
| | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap_resource() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200429025426.167664-1-weiyongjun1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-amd: fix warningSanjay R Mehta2020-04-281-1/+1
| | | | | | | | | | | | | | | | | | remove unused variable "opcode" Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1588049801-37995-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-amd: Add AMD SPI controller driver supportSanjay R Mehta2020-04-273-0/+340
| | | | | | | | | | | | | | | | | | | | This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-fsl-dspi: Adding shutdown hookPeng Ma2020-04-241-0/+23
| | | | | | | | | | | | | | | | | | | | We need to ensure dspi controller could be stopped in order for kexec to start the next kernel. So add the shutdown operation support. Signed-off-by: Peng Ma <peng.ma@nxp.com> Link: https://lore.kernel.org/r/20200424061216.27445-1-peng.ma@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-mem: Fix Dual/Quad modes on Octal-capable devicesGeert Uytterhoeven2020-04-231-4/+6
| | | | | | | | | | | | | | | | | | | | | | Currently buswidths 2 and 4 are rejected for a device that advertises Octal capabilities. Allow these buswidths, just like is done for buswidth 2 and Quad-capable devices. Fixes: b12a084c8729ef42 ("spi: spi-mem: add support for octal mode I/O data transfer") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200416101418.14379-1-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-fsl-qspi: Fix return value check of devm_ioremap() in probeWei Yongjun2020-04-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 858e26a515c2 ("spi: spi-fsl-qspi: Reduce devm_ioremap size to 4 times AHB buffer size") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/20200422014543.111070-1-weiyongjun1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllersKamal Dasu2020-04-211-1/+7
| | | | | | | | | | | | | | | | | | | | Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-10-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm-qspi: add support for MSPI sys clk 108MhzKamal Dasu2020-04-211-0/+44
| | | | | | | | | | | | | | | | | | Adding support for MSPI sys clk 108Mhz available on 7216 and 7278 BRCMSTB SoCs. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-9-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm-qspi: Use fastbr setting to allow faster MSPI speedsKamal Dasu2020-04-211-3/+33
| | | | | | | | | | | | | | | | | | | | Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of 1-7, while the default value prohibits these values and requires a minimum clock divider value of 8. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-8-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm-qspi: Handle lack of MSPI_REV offsetFlorian Fainelli2020-04-211-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | Older MIPS chips have a QSPI/MSPI controller that does not have the MSPI_REV offset, reading from that offset will cause a bus error. Match their compatible string and do not perform a read from that register in that case. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-4-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: orion: Convert to use GPIO descriptorsLinus Walleij2020-04-211-54/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the Orion SPI master to use GPIO descriptors. The SPI core will obtain and manage the CS GPIOs, if any are defined. I make one sematic change: when a certain chip select is using a GPIO line instead of the native CS I simply just enable the 1:1 mapped native CS that would have been used if the GPIO was not there. As we set the SPI_MASTER_GPIO_SS the .set_cs() callback will be called for all chip selects whether native or not, and the important thing for the driver is that the previous native chip select (if any) is deasserted, which other chip select is asserted instead does not really matter. The previous code went to great lengths to ascertain that the first hw CS which was hiding behind a GPIO line was used for all cases when the line is not using native chip select but this should not matter at all, just use the one "underneath" the GPIO at all times. When a GPIO is used for CS, the SPI_CS_HIGH flag is enforced, so the native chip select is also inverted. But that should not matter since we are not using it anyways. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Tomas Paukrt <tomaspaukrt@email.cz> Cc: Jan Kundrát <jan.kundrat@cesnet.cz> Link: https://lore.kernel.org/r/20200415175613.220767-1-linus.walleij@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: hisi-sfc-v3xx: add error check after per operationYicong Yang2020-04-171-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The controller may receive instructions of accessing protected address, or may perform failed page program. These operations will not succeed and the controller will receive interrupts when such failure occur. Previously we don't check the interrupts and return 0 even if such operation fails. Check the interrupts after per command and inform the user if there is an error. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Acked-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1587109707-23597-1-git-send-email-yangyicong@hisilicon.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: stm32-qspi: Add pm_runtime supportPatrice Chotard2020-04-171-4/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, STM32_AUTOSUSPEND_DELAY is set to -1 which has for effect to prevent runtime suspends. Runtime suspends can be activated by setting autosuspend_delay_ms using sysfs entry : echo {delay_in_ms} > /sys/devices/platform/soc/58003000.spi/power/autosusp end_delay_ms) Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Link: https://lore.kernel.org/r/20200417121241.6473-1-patrice.chotard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | Merge series "Cleanup chip info in spi-dw driver" from Clement Leger ↵Mark Brown2020-04-162-68/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <cleger@kalray.eu>: Some mechanisms have no more user, and as such code paths are unused. Remove these code paths and associated structs members. Clement Leger (2): spi: dw: remove unused dw_spi_chip handling spi: dw: remove cs_control and poll_mode members from chip_data drivers/spi/spi-dw.c | 57 +------------------------------------------- drivers/spi/spi-dw.h | 12 ---------- 2 files changed, 1 insertion(+), 68 deletions(-) -- 2.17.1
| * | spi: dw: remove cs_control and poll_mode members from chip_dataClement Leger2020-04-161-40/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since these members were initialized only with previous dw_spi_chip struct members and that there is no user anymore, remove them. Along this removal, remove code path which were using these members. Signed-off-by: Clement Leger <cleger@kalray.eu> Link: https://lore.kernel.org/r/20200416110916.22633-2-cleger@kalray.eu Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: dw: remove unused dw_spi_chip handlingClement Leger2020-04-162-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The path of code using this struct is unused since there is no more user of this. Remove code and struct definition. Signed-off-by: Clement Leger <cleger@kalray.eu> Link: https://lore.kernel.org/r/20200416110916.22633-1-cleger@kalray.eu Signed-off-by: Mark Brown <broonie@kernel.org>
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