| Commit message (Collapse) | Author | Age | Files | Lines |
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pm_runtime_get_sync() returns 1 if !CONFIG_PM_RUNTIME.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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In case we are doing DMA transfer and the size of the buffer is not multiple
of 4 bytes the driver truncates that to 4-byte boundary and tries to handle
remaining bytes using PIO.
Or that is what it tried to do. What actually happens is that it calls
ALIGN() to the buffer size which aligns it to the next 4-byte boundary
(doesn't truncate). Doing this results 1-3 bytes extra to be transferred.
Furthermore we handle remaining bytes using PIO which results one extra
byte to be transferred. In worst case the driver transfers 4 extra bytes.
While investigating this it turned out that the DMA hardware doesn't even
have such limitation so we can solve this by dropping the code that tries
to handle unaligned bytes.
Reported-by: Chiau Ee Chew <chiau.ee.chew@intel.com>
Reported-by: Hock Leong Kweh <hock.leong.kweh@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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If we fail to create the master queue for some reason we should not attempt
to clean it up since attempting to stop a kthread that was not created will
hang and it's just generally bad practice. Unfortunately at present we call
spi_destroy_queue() even in cases where the creation fails.
Fix this by fixing the error handling in spi_master_initialize_queue() so
that we only flag the master as queued or destroy the queue if creation
succeeded. The change to the flag is done since the general master
cleanup uses this to destroy the queue.
Reported-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
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If NO_DMA=y:
drivers/built-in.o: In function `spi_map_buf':
spi.c:(.text+0x21bc60): undefined reference to `dma_map_sg'
drivers/built-in.o: In function `spi_unmap_buf.isra.33':
spi.c:(.text+0x21c32e): undefined reference to `dma_unmap_sg'
make[3]: *** [vmlinux] Error 1
Protect the DMA code by #ifdef CONFIG_HAS_DMA to fix this:
- Extract __spi_map_msg() from spi_map_msg(),
- Provide dummy definitions of __spi_map_msg() and spi_unmap_msg() if
!CONFIG_HAS_DMA.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The availability of SPI Dual or Quad Transfer Mode as indicated by the
"spi-tx-bus-width" and "spi-rx-bus-width" properties in the device tree is
a hardware property of the SPI master, SPI slave, and board wiring. Hence
the SPI core should not reject an SPI slave because an SPI master driver
doesn't (yet) support Dual or Quad Transfer Mode.
Change the lack of Dual or Quad Transfer Mode support in the SPI master
driver from an error condition to a warning condition, and ignore the
unsupported mode bits, falling back to Single Transfer Mode, to avoid
breakages when running old kernels with new device trees.
Fixes: f477b7fb13df (spi: DUAL and QUAD support)
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
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'spi/fix/hspi' and 'spi/fix/sirf' into spi-linus
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orignal GPIO chipslect is not standard because it don't take care to the
chipselect signal: BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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SPI bitbang supply "chipselect" interface for change chip-select line
, in the SiRFSoC SPI controller, we need to enable "SPI_CS_IO_MODE",
otherwise, spi_sirfsoc_chipselect() has no effect.
now the driver is working is because SPI controller will control CS
automatically without SPI_CS_IO_MODE. this patch makes the CS controller
really controlled by software.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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the old code uses wrong marco - SIRFSOC_SPI_FIFO_FULL is not for
FIFO interrupt status, it is for FIFO status. here in the ISR,
SIRFSOC_SPI_TXFIFO_EMPTY is the right bit for SPI TXFIFO interrupt
status.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Rather than requesting the shyway_clk call clk_get with
the device and a NULL con_id.
This is in keeping with the way that clk_get() is called
on other drivers used by Renesas Gen 1 SoCs. And I believe
it is compatible with supplying clocks via DT, unlike the current code.
It appears to me that the two uses of this driver are
the r8a7778 and r8a7779 SoCs.
The r8a7779 already has clocks setup to allow this driver to continue to work
with this change applied.
The r8a7778 has clocks incorrectly setup to allow this driver to continue
to work with this change applied. This problem is addressed in
"ARM: shmobile: r8a7778: Use clks as MSTP007 parent" which is thus
a pre-requisite of this patch.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@linaro.org>
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should include linux/gpio.h
Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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atmel_spi_lock does a spin_lock_irqsave, so we need to renable the
interrupts when we want to schedule.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A few driver specific fixes, the main one being the fix for handling
of complete callbacks that are open coded in individual drivers to
allow callers to omit the completion. As we move things into the core
that sort of issue should become less and less common"
* tag 'spi-v3.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: qup: Depend on ARCH_QCOM
spi: efm32: Update binding document to make "efm32,location" property optional
spi: omap2-mcspi: Convert to use devm_kcalloc
spi: Always check complete callback before calling it
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'spi/fix/omap2-mcspi' and 'spi/fix/qup' into spi-linus
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Commit 8fc1b0f87d9f ("ARM: qcom: Split Qualcomm support into legacy and
multiplatform") removed Kconfig symbol ARCH_MSM_DT. But that commit
left one (optional) dependency on ARCH_MSM_DT untouched.
Three Kconfig symbols used to depend on ARCH_MSM_DT: ARCH_MSM8X60,
ARCH_MSM8960, and ARCH_MSM8974. These three symbols now depend on
ARCH_QCOM. So it appears this driver needs to depend on ARCH_QCOM too.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This saves a few unwind code and return proper error if devm_kcalloc fails.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Since commit 1e25cd4729bd "spi: Do not require a completion", this checking is
required to prevent NULL pointer dereference.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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git://git.linux-mips.org/pub/scm/ralf/upstream-sfr
Pull MIPS updates from Ralf Baechle:
- Support for Imgtec's Aptiv family of MIPS cores.
- Improved detection of BCM47xx configurations.
- Fix hiberation for certain configurations.
- Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
systems.
- Detection and support for the MIPS P5600 core.
- A few more random fixes that didn't make 3.14.
- Support for the EVA Extended Virtual Addressing
- Switch Alchemy to the platform PATA driver
- Complete unification of Alchemy support
- Allow availability of I/O cache coherency to be runtime detected
- Improvments to multiprocessing support for Imgtec platforms
- A few microoptimizations
- Cleanups of FPU support
- Paul Gortmaker's fixes for the init stuff
- Support for seccomp
* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
MIPS: CPC: Use __raw_ memory access functions
MIPS: CM: use __raw_ memory access functions
MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
MIPS: Malta: GIC IPIs may be used without MT
MIPS: smp-mt: Use common GIC IPI implementation
MIPS: smp-cmp: Remove incorrect core number probe
MIPS: Fix gigaton of warning building with microMIPS.
MIPS: Fix core number detection for MT cores
MIPS: MT: core_nvpes function to retrieve VPE count
MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
MIPS: Lasat: Replace del_timer by del_timer_sync
MIPS: Malta: Setup PM I/O region on boot
MIPS: Loongson: Add a Loongson-3 default config file
MIPS: Loongson 3: Add CPU hotplug support
MIPS: Loongson 3: Add Loongson-3 SMP support
MIPS: Loongson: Add Loongson-3 Kconfig options
MIPS: Loongson: Add swiotlb to support All-Memory DMA
MIPS: Loongson 3: Add serial port support
MIPS: Loongson 3: Add IRQ init and dispatch support
MIPS: Loongson 3: Add HT-linked PCI support
...
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This patch merges support for all DB1xxx and PB1xxx
boards into a single image, along with a new single defconfig
for them.
Run-tested on DB1300 and DB1500.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6577/
Patchwork: https://patchwork.linux-mips.org/patch/6659/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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into spi-next
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This helps increasing build testing coverage.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This simple SPI master controller is built into xtfpga bitstreams. It
always transfers 16 bit words in SPI mode 0, automatically asserting CS
on transfer start and deasserting on end.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Remove unnecessary space in order to fix the following
checkpatch issues.
WARNING: Unnecessary space after function pointer name
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Reviewed-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Set bits_per_word_mask so spi core will reject transfers that attempt to use
an unsupported bits_per_word value.
spi_bitbang requires custom setup_transfer() to be defined if there is a
custom txrx_bufs(). Thus keep the empty xilinx_spi_setup_transfer() function
in the code.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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'spi/topic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
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Don't wait indefinitely for transfers to complete but time out after 10ms
more than we expect the transfer to take on the wire.
Signed-off-by: Mark Brown <broonie@linaro.org>
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In the implementation of __spi_validate(), spi core will set transfer
bits_per_word and max speed as spi device default if it is not set for
this transfer. So we can remove the same logic in spi_xcomm_setup_transfer().
Also remove a redundant code to initialize is_first variable.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
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spi core will handle validating transfer length since commit 4d94bd21b333
"spi: core: Validate length of the transfers in message".
So remove the same checking in this driver.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Use devm_ioremap_resource() in order to make the code simpler,
and remove redundant return value check of platform_get_resource()
because the value is checked by devm_ioremap_resource().
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
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By setting master->max_speed_hz and master->min_speed_hz, spi core will handle
checking transfer speed. Then we can remove the same checking in this driver.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
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If during a SPI transfer with len larger than PCH_MAX_FIFO_DEPTH and the
IRQ handler happens to be called when the transmit FIFO is already empty,
and SPSR_FI_BIT is set consequently, the message
"spi_master spi32766: pch_spi_handler_sub : Transfer is not completed"
is spammed to the systemlog, because tx_index has already increased
further due to the next bytes to be written. This case is uncritical as
new bytes have already been written.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Ensure all registered platform devices are unregistered on probe() error paths.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Set "master->max_speed_hz = PCH_MAX_BAUDRATE" then we can remove pch_spi_setup.
In additional, pspi->max_speed_hz will never be 0 because it's default value
will be set to master->max_speed_hz.
Also remove list_empty checking in pch_spi_transfer() because the checking is
done by spi core.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The tnetv107x platform is getting removed, so this driver
will not be needed any more.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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mmap resource requirement is only for memory mapped operations.
If the user does not populate mmap resource, dont call return,
instead we go on for normal spi mode operations.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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For better readability, and then we can remove the comment for last transfer.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This controller only supports 8 bits word length.
Set bits_per_word_mask so spi core will reject transfers that attempt to use
an unsupported bits_per_word value.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This controller only supports 8 bits word length.
Set bits_per_word_mask so spi core will reject transfers that attempt to use
an unsupported bits_per_word value.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
controller.
Unfortunately, this SPI controller, even though quite similar, is significantly
different from the recently supported A31 SPI controller (different registers
offset, split/merged registers, etc.). Supporting both controllers in a single
driver would be unreasonable, hence the addition of a new driver.
Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Current code in sun6i_spi_set_cs() actually clears CPHA and CPOL bits which is
obvious wrong. The define for SUN6I_TFR_CTL_CS_MASK is wrong. Fix it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Signed-off-by: Mark Brown <broonie@linaro.org>
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The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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'spi/topic/sh-hspi', 'spi/topic/sh-msiof', 'spi/topic/sh-sci', 'spi/topic/sirf' and 'spi/topic/spidev' into spi-next
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Add support for Dual/Quad SPI Transfers to the spidev API.
As this uses SPI mode bits that don't fit in a single byte, two new
ioctls (SPI_IOC_RD_MODE32 and SPI_IOC_WR_MODE32) are introduced.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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In commit f477b7fb13df2b843997559ff34e87d054ba6538 ("spi: DUAL and QUAD
support"), spi_device.mode was enlarged from 8 to 16 bits.
However, the spidev code still only saved 8 bits of data. If a spidev
SPI_IOC_WR_MODE or SPI_IOC_WR_LSB_FIRST request failed, only the lower 8
bits of the SPI mode were restored, inadvertently clearing the upper 8
bits, possibly disabling Quad or Dual SPI transfers for the device.
Save up to 32 bits to fix this.
For SPI_IOC_WR_MODE this is probably not so important, as it doesn't allow
setting Quad or Dual mode anyway, but SPI_IOC_WR_LSB_FIRST is used to just
set or clear a single bit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This is required since commit 2025172e3280 "spi/bitbang: Use core message pump".
spi-bitbang now uses core message pump, so it needs to call spi_master_suspend/
spi_master_resume to stop/start the queue while suspend/resume.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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