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broadsheetfb.c
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Author
Files
Lines
2013-01-31
drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too
Ville Syrjälä
1
-2
/
+1
2013-01-31
drm/i915: Kill IS_DISPLAYREG()
Ville Syrjälä
1
-103
/
+1
2013-01-31
drm/i915: Introduce i915_vgacntrl_reg()
Ville Syrjälä
4
-20
/
+16
2013-01-31
drm/i915: gen6_gmch_remove can be static
Changlong Xie
1
-1
/
+1
2013-01-31
drm/i915: dynamic Haswell display power well support
Daniel Vetter
2
-1
/
+38
2013-01-31
drm/i915: check the power down well on assert_pipe()
Paulo Zanoni
1
-3
/
+9
2013-01-31
drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A
Paulo Zanoni
1
-6
/
+10
2013-01-31
drm/i915: don't run hsw power well code on !hsw
Daniel Vetter
1
-0
/
+3
2013-01-31
drm/i915: kill cargo-culted locking from power well code
Daniel Vetter
1
-4
/
+0
2013-01-31
drm/i915: Only run idle processing from i915_gem_retire_requests_worker
Chris Wilson
3
-14
/
+4
2013-01-31
drm/i915: Fix CAGF for HSW
Ben Widawsky
2
-3
/
+9
2013-01-31
drm/i915: Reclaim GTT space for failed PPGTT
Ben Widawsky
1
-17
/
+16
2013-01-31
drm/i915: remove intel_gtt structure
Ben Widawsky
5
-54
/
+33
2013-01-31
drm/i915: Add probe and remove to the gtt ops
Ben Widawsky
3
-79
/
+114
2013-01-31
drm/i915: extract hw ppgtt setup/cleanup code
Daniel Vetter
2
-24
/
+45
2013-01-31
drm/i915: pte_encode is gen6+
Daniel Vetter
1
-10
/
+14
2013-01-31
drm/i915: vfuncs for ppgtt
Daniel Vetter
2
-56
/
+65
2013-01-31
drm/i915: vfuncs for gtt_clear_range/insert_entries
Daniel Vetter
2
-59
/
+83
2013-01-31
drm/i915: Error state should print /sys/kernel/debug
Ben Widawsky
1
-1
/
+2
2013-01-31
drm/i915: move DP save/restore into i915_ums.c
Daniel Vetter
2
-28
/
+25
2013-01-31
drm/i915: dont save/restore VGA state for kms
Daniel Vetter
3
-23
/
+28
2013-01-31
drm/i915: extract ums suspend/resume into i915_ums.c
Daniel Vetter
4
-452
/
+485
2013-01-28
drm/i915: move modeset checks out of save/restore_modeset_reg
Daniel Vetter
1
-23
/
+15
2013-01-28
drm/i915: Implement WaVSRefCountFullforceMissDisable
Ben Widawsky
2
-0
/
+5
2013-01-28
drm/i915: turn on the power well before suspending
Paulo Zanoni
3
-1
/
+4
2013-01-28
drm/i915: set TRANSCODER_EDP even earlier
Paulo Zanoni
1
-5
/
+5
2013-01-27
drm/i915: fixup per-crtc locking in intel_release_load_detect_pipe
Daniel Vetter
1
-0
/
+1
2013-01-26
drm/i915: only disable enabled planes on intel_fb_restore_mode
Paulo Zanoni
1
-1
/
+2
2013-01-26
drm/i915: fix intel_init_power_wells
Paulo Zanoni
4
-26
/
+46
2013-01-26
drm/i915: SWF screatch registers need an offset on VLV
Ville Syrjälä
1
-13
/
+13
2013-01-26
drm/i915: Include display_mmio_offset in sequencer index/data registers
Ville Syrjälä
1
-2
/
+8
2013-01-26
drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV
Ville Syrjälä
1
-8
/
+8
2013-01-26
drm/i915: VLV doesn't have SDVO
Ville Syrjälä
1
-7
/
+2
2013-01-26
drm/i915: Always use adpa_reg
Ville Syrjälä
1
-14
/
+15
2013-01-26
drm/i915: PLL registers need an offset on VLV
Ville Syrjälä
1
-4
/
+4
2013-01-24
drm/i915: Set display_mmio_offset for VLV
Ville Syrjälä
1
-0
/
+2
2013-01-24
drm/i915: GPIO/GMBUS registers need an offset on VLV
Ville Syrjälä
1
-0
/
+2
2013-01-24
drm/i915: DPIO registers are VLV only and need an offset
Ville Syrjälä
1
-4
/
+6
2013-01-24
drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
Ville Syrjälä
1
-5
/
+5
2013-01-24
drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
Ville Syrjälä
1
-1
/
+1
2013-01-24
drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
Ville Syrjälä
1
-1
/
+1
2013-01-24
drm/i915: Pipe palette registers need an offset on VLV
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Pipe timing registers need an offset on VLV
Ville Syrjälä
1
-18
/
+18
2013-01-24
drm/i915: PORT_HOTPLUG registers need an offset on VLV
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Panel fitter registers need an offset on VLV
Ville Syrjälä
1
-3
/
+3
2013-01-24
drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: DSPFW registers need an offset on VLV
Ville Syrjälä
1
-3
/
+3
2013-01-24
drm/i915: VLV_DDL is VLV only and needs an offset
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Cursor registers need an offset on VLV
Ville Syrjälä
1
-6
/
+6
2013-01-24
drm/i915: Pipe registers need an offset on VLV
Ville Syrjälä
1
-10
/
+10
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