| Commit message (Expand) | Author | Files | Lines | |
|---|---|---|---|---|
| 2015-07-16 | clk: tegra: Add the DFLL as a possible parent of the cclk_g clock | Tuomas Tynkkynen | 1 | -1/+3 |
| 2015-07-16 | clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend | Tuomas Tynkkynen | 1 | -0/+14 |
| 2015-07-16 | clk: tegra: Add Tegra124 DFLL clocksource platform driver | Tuomas Tynkkynen | 4 | -4/+172 |
| 2015-07-16 | clk: tegra: Add DFLL DVCO reset control for Tegra124 | Paul Walmsley | 2 | -0/+80 |
| 2015-07-16 | clk: tegra: Introduce ability for SoC-specific reset control callbacks | Mikko Perttunen | 2 | -8/+34 |
| 2015-07-16 | clk: tegra: Add functions for parsing CVB tables | Tuomas Tynkkynen | 3 | -0/+208 |
| 2015-07-16 | clk: tegra: Add closed loop support for the DFLL | Tuomas Tynkkynen | 1 | -3/+663 |
| 2015-07-16 | clk: tegra: Add library for the DFLL clock source (open-loop mode) | Tuomas Tynkkynen | 3 | -0/+1150 |
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