summaryrefslogtreecommitdiffstats
path: root/drivers (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'mcp23s08' into develLinus Walleij2017-05-235-268/+411
|\
| * pinctrl: mcp23s08: drop comment about missing irq supportSebastian Reichel2017-05-231-17/+2
| | | | | | | | | | | | | | | | The driver supports using mcp23xxx as interrupt controller, so let's drop all comments stating otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify spi_present_mask handlingSebastian Reichel2017-05-231-19/+10
| | | | | | | | | | Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: generalize irq property handlingSebastian Reichel2017-05-231-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves irq property handling from spi/i2c specific code into the generic mcp23s08_probe_one. This is possible because the device properties are named equally. As a side-effect this drops support for setting the properties via pdata, which has no mainline users. If boardcode wants to enable the chip as interrupt controller it can attach the device properties instead. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify spi pdata handlingSebastian Reichel2017-05-231-35/+32
| | | | | | | | | | | | | | | | Simplify spi pdata handling, so that it uses pdata when available and falls back to reading device properties otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: simplify i2c pdata handlingSebastian Reichel2017-05-231-19/+7
| | | | | | | | | | | | | | | | Simplify i2c pdata handling, so that it uses pdata when available and falls back to reading device properties otherwise. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: switch to devm_gpiochip_add_dataSebastian Reichel2017-05-231-38/+2
| | | | | | | | | | | | | | | | Switching to devm_gpiochip_add_data simplifies the driver's cleanup routine and safes a few loc. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: use managed kzalloc for mcpSebastian Reichel2017-05-231-8/+2
| | | | | | | | | | | | | | | | Let's remove a few lines of code by using managed memory for mcp variable. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: irq mapping is already doneSebastian Reichel2017-05-231-4/+0
| | | | | | | | | | | | | | | | i2c-core and spi-core already assign the irq, so we can drop the additional call from the mcp driver. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: drop OF_GPIO dependencySebastian Reichel2017-05-231-1/+0
| | | | | | | | | | | | | | | | The driver compiles & works perfectly fine without OF_GPIO on x86, so lets drop the dependency. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: switch to regmap cachingSebastian Reichel2017-05-231-95/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using custom caching, this switches to regmap based caching. Before the conversion the debugfs file used uncached values, so that it was easily possible to see power-loss related problems. The new code will check and recover at this place. The patch will also ensure, that irqs are not cleared by checking register status in debugfs. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: drop pullup config from pdataSebastian Reichel2017-05-231-7/+0
| | | | | | | | | | | | | | | | | | mcp23s08 support configuration of the pullups using the pinconf framework. This removes the custom pullup configuration from platform data, which has no upstream users. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: add pinconf supportSebastian Reichel2017-05-232-24/+176
| | | | | | | | | | | | | | | | | | mcp23xxx device have configurable 100k pullup resistors. This adds support for enabling them using pinctrl's pinconf interface. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * gpio: mcp23s08: move to pinctrlSebastian Reichel2017-05-235-18/+14
| | | | | | | | | | | | | | | | | | | | This moves the mcp23s08 driver from gpio to pinctrl. Actual pinctrl support for configuration of the pull-up resistors follows in its own patch. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge branch 'ingenic' into develLinus Walleij2017-05-2210-191/+1276
|\ \
| * | mtd: nand: jz4740: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, this NAND driver would set itself the configuration of the chip-select pins for the various NAND banks. Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | fbdev: jz4740-fb: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-101/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pwm: jz4740: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. One inherent problem of this new approach is that the pinctrl framework does not allow us to configure each pin on demand, when the various PWM channels are requested or released. For instance, the PWM channels can be configured from sysfs, which would require all PWM pins to be configured properly beforehand for the PWM function, eventually causing conflicts with other platform or board drivers. The proper solution here would be to modify the pwm-jz4740 driver to handle only one PWM channel, and create an instance of this driver for each one of the 8 PWM channels. Then, it could use the pinctrl framework to dynamically configure the PWM pin it controls. Until this can be done, the only jz4740 board supported upstream (Qi lb60) can configure all of its connected PWM pins in PWM function mode, since those are not used by other drivers nor by GPIOs on the board. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | mmc: jz4740: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-39/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | gpio: Add gpio-ingenic driverPaul Cercueil2017-05-223-0/+405
| | | | | | | | | | | | | | | | | | | | | | | | This driver handles the GPIOs of all the Ingenic JZ47xx SoCs currently supported by the upsteam Linux kernel. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCsPaul Cercueil2017-05-223-0/+862
| |/ | | | | | | | | | | | | | | This driver handles pin configuration and pin muxing for the JZ4740 and JZ4780 SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: When claiming hog, skip maps not served by same deviceNikita Yushchenko2017-05-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When pinctrl device registers, it automatically claims hogs, that is, maps that pinctrl device serves for itself. It is possible that in addition to SoC's pinctrl device, other pinctrl devices get registered. E.g. some gpio expander devies are registered as pinctrl devices. For such devices, pinctrl maps could be defined that set up SoC's pins (e.g. interrupt pin for gpio expander). Such a map will have target device set to gpio expander. Here is device tree snippet that causes this scenario: &i2c0 { sx1503@20 { compatible = "semtech,sx1503q"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sx1503_20>; ... }; }; ... &iomuxc { pinctrl_sx1503_20: pinctrl-sx1503-20 { fsl,pins = < VF610_PAD_PTB1__GPIO_23 0x219d >; }; }; Such a map will have target device set to gpio expander. However is not a hog, it is a regular map that is claimed by core before gpio expander device is probed. Thus when looking for hogs, it is not enough to check that map's target device is set to pinctrl device being registered. Need also check that map's control device is also set to the same. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add soc specific mux_mode mask and shift propertyDong Aisheng2017-05-223-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support. One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference. Cc: Stefan Agner <stefan@agner.ch> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add generic pin config core supportDong Aisheng2017-05-223-11/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform. Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently. In order to cope with some special case, a platform specific fixup() function is also available to use. Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic. Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG caseDong Aisheng2017-05-221-4/+8
| | | | | | | | | | | | | | | | | | | | The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it. Fixes: bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: Check for memory allocation failureChristophe JAILLET2017-05-221-2/+3
| | | | | | | | | | | | | | | | | | | | If 'devm_kzalloc' fails, a NULL pointer will be dereferenced. Return -ENOMEM instead, as done for the other memory allocation just a few lines below. BTW, change the 'devm_kzalloc' into a 'devm_kcalloc'. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: reuse pinctrl driver for mt7623Sean Wang2017-05-225-2324/+2
| | | | | | | | | | | | | | | | | | | | | | mt7623 pinctrl hardware can be compatible with mt2701 driver, so the patch lets the pinctrl on mt7623 SoC reuse the driver and deletes those redundant ones. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add the AO HDMI CEC pinMartin Blumenstingl2017-05-221-0/+9
| | | | | | | | | | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add support for the AO remote output pinMartin Blumenstingl2017-05-221-1/+3
| | | | | | | | | | | | | | | | This adds another missing pin found in the Meson8 SoCs. Currently there's no driver which would use this pin yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add support for the I2S and SPDIF pinsMartin Blumenstingl2017-05-221-0/+52
| | | | | | | | | | | | | | | | This adds support for the I2S and SPDIF input and output pins, similar to what we have on GXBB and GXL. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8: add the PWM pinsMartin Blumenstingl2017-05-221-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds the missing pins for the PWM controllers found in Amlogic Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D, PWM_E and PWM_F controllers. There is an additional PWM function with the name PWM_VS in the vendor kernel sources which seems to be used for external video input. Thus it's not part of this change as the IP block behind the pwm-meson driver is not responsible for these pins. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Adjust nine checks for null pointersMarkus Elfring2017-05-221-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written … Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Use seq_putc() in pinctrl_maps_show()Markus Elfring2017-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add spaces for better code readabilityMarkus Elfring2017-05-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. CHECK: spaces preferred around that '+' (ctx:VxV) Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Combine substrings for a message in pin_config_group_get()Markus Elfring2017-05-221-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. WARNING: quoted string split across lines Thus fix the affected source code place. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Adjust five checks for null pointersMarkus Elfring2017-05-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The script “checkpatch.pl” pointed information out like the following. Comparison to NULL could be written !… Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Replace two seq_printf() calls by seq_puts() in pinconf_show_map()Markus Elfring2017-05-221-2/+2
| | | | | | | | | | | | | | | | | | | | Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/amd: Update contact information for AMD pinctrl/amdShyam Sundar S K2017-05-221-0/+4
| | | | | | | | | | | | | | | | | | Updating the point of contact for AMD GPIO driver. Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Cc: Ken Xue <Ken.Xue@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Use seq_putc() in three functionsMarkus Elfring2017-05-221-5/+3
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: armada-37xx: Add irqchip supportGregory CLEMENT2017-05-221-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed is classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller. But we do not take advantage of this and use the chained irq with all of them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: remove unneeded (void *) casts in of_match_tableMasahiro Yamada2017-05-221-11/+11
| | | | | | | | | | | | | | | | of_device_id::data is an opaque pointer. No explicit cast is needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add ZTE ZX pinctrl driver supportShawn Guo2017-05-227-0/+1594
|/ | | | | | | | | | | | | | | | | | | | | | The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of a main controller and an auxiliary one. For example, on ZX296718 SoC, the main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both controllers work together to control pin multiplexing and configuration. For most of pins, the pinmux function is controlled by main controller only, and this type of pins are meant by term 'TOP pins'. For other pins, the pinmux is controlled by both main and auxiliary controllers, as the available multiplexing functions for the pin spread in both controllers. This type of pins are called 'AON pins'. Though pinmux implementation is quite different, pinconf is same for both types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG on ZX296718. The patch adds the ZTE ZX core pinctrl driver to support this hybrid pin controller as well as ZX296718 SoC specific pin data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2017-05-211-7/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "A set of small fixes for the irq subsystem: - Cure a data ordering problem with chained interrupts - Three small fixlets for the mbigen irq chip" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: genirq: Fix chained interrupt data ordering irqchip/mbigen: Fix the clear register offset calculation irqchip/mbigen: Fix potential NULL dereferencing irqchip/mbigen: Fix memory mapping code
| * irqchip/mbigen: Fix the clear register offset calculationMaJun2017-05-121-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register array offset for clearing an interrupt is calculated by: offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / 32; This is wrong because the clear register array includes the reserved interrupts. So the clear operation ends up in the wrong register. This went unnoticed so far, because the hardware clears the real bit through a timeout mechanism when the hardware is configured in debug mode. That debug mode was enabled on early generations of the hardware, so the problem was papered over. On newer hardware with updated firmware the debug mode was disabled, so the bits did not get cleared which causes the system to malfunction. Remove the subtraction of RESERVED_IRQ_PER_MBIGEN_CHIP, so the correct register is accessed. [ tglx: Rewrote changelog ] Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operation functions") Signed-off-by: MaJun <majun258@huawei.com> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Kefeng Wang <wangkefeng.wang@huawei.com> Cc: linuxarm@huawei.com Cc: Wei Yongjun <weiyongjun1@huawei.com> Link: http://lkml.kernel.org/r/1494561328-39514-4-git-send-email-guohanjun@huawei.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * irqchip/mbigen: Fix potential NULL dereferencingHanjun Guo2017-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Kefeng Wang <wangkefeng.wang@huawei.com> Cc: linuxarm@huawei.com Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: MaJun <majun258@huawei.com> Link: http://lkml.kernel.org/r/1494561328-39514-3-git-send-email-guohanjun@huawei.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * irqchip/mbigen: Fix memory mapping codeHanjun Guo2017-05-121-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some mbigens share memory regions, and devm_ioremap_resource does not allow to share resources which will break the probe of mbigen, in opposition to devm_ioremap. This patch restores back usage of devm_ioremap function, but with proper error handling and logging. Fixes: 216646e4d82e ("irqchip/mbigen: Fix return value check in mbigen_device_probe()") Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Kefeng Wang <wangkefeng.wang@huawei.com> Cc: linuxarm@huawei.com Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: MaJun <majun258@huawei.com> Link: http://lkml.kernel.org/r/1494561328-39514-2-git-send-email-guohanjun@huawei.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | Merge branch 'for-linus' of git://git.kernel.dk/linux-blockLinus Torvalds2017-05-2110-21/+45
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull block fixes from Jens Axboe: "A small collection of fixes that should go into this cycle. - a pull request from Christoph for NVMe, which ended up being manually applied to avoid pulling in newer bits in master. Mostly fibre channel fixes from James, but also a few fixes from Jon and Vijay - a pull request from Konrad, with just a single fix for xen-blkback from Gustavo. - a fuseblk bdi fix from Jan, fixing a regression in this series with the dynamic backing devices. - a blktrace fix from Shaohua, replacing sscanf() with kstrtoull(). - a request leak fix for drbd from Lars, fixing a regression in the last series with the kref changes. This will go to stable as well" * 'for-linus' of git://git.kernel.dk/linux-block: nvmet: release the sq ref on rdma read errors nvmet-fc: remove target cpu scheduling flag nvme-fc: stop queues on error detection nvme-fc: require target or discovery role for fc-nvme targets nvme-fc: correct port role bits nvme: unmap CMB and remove sysfs file in reset path blktrace: fix integer parse fuseblk: Fix warning in super_setup_bdi_name() block: xen-blkback: add null check to avoid null pointer dereference drbd: fix request leak introduced by locking/atomic, kref: Kill kref_sub()
| * | nvmet: release the sq ref on rdma read errorsVijay Immanuel2017-05-203-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On rdma read errors, release the sq ref that was taken when the req was initialized. This avoids a hang in nvmet_sq_destroy() when the queue is being freed. Signed-off-by: Vijay Immanuel <vijayi@attalasystems.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@fb.com>
| * | nvmet-fc: remove target cpu scheduling flagJames Smart2017-05-203-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove NVMET_FCTGTFEAT_NEEDS_CMD_CPUSCHED. It's unnecessary. Signed-off-by: James Smart <james.smart@broadcom.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@fb.com>
| * | nvme-fc: stop queues on error detectionJames Smart2017-05-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per the recommendation by Sagi on: http://lists.infradead.org/pipermail/linux-nvme/2017-April/009261.html Rather than waiting for reset work thread to stop queues and abort the ios, immediately stop the queues on error detection. Reset thread will restop the queues (as it's called on other paths), but it does not appear to have a side effect. Signed-off-by: James Smart <james.smart@broadcom.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@fb.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-02 10:41:07 +0100