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* clk: versatile: free icst on error returnColin Ian King2014-05-311-0/+1
| | | | | | | | | commit a183da63 introduced a new error return path that does not kfree icst if the kmemdup of desc->params fails. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Return error pointers for unimplemented clocksStephen Boyd2014-05-291-1/+3
| | | | | | | | | | | Not all clocks are implemented but client drivers can still request them. Currently we will return a NULL pointer to them if the clock isn't implemented in software but NULL pointers are valid clock pointers. Return an error pointer so that driver's don't proceed without a clock they may actually need. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Support msm8974pro global clock control hardwareStephen Boyd2014-05-291-6/+124
| | | | | | | | | A new PLL (gpll4) is added on msm8974 PRO devices to support a faster sdc1 clock rate. Add support for this and the two new sdcc cal clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Properly support display clocks on msm8974Stephen Boyd2014-05-291-51/+54
| | | | | | | | | | | | The display clocks all source from dedicated phy PLLs within their respective multimedia hardware block. Hook up these PLLs to the display clocks with the appropriate parent mappings, clock flags, and the appropriate clock ops. This should allow the display clocks to work once the appropriate phy PLL driver registers their PLL clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Support display RCG clocksStephen Boyd2014-05-292-15/+287
| | | | | | | | | Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Return highest rate when round_rate() exceeds planStephen Boyd2014-05-291-1/+2
| | | | | | | | | | | | Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix mmcc-8974's PLL configurationsStephen Boyd2014-05-291-5/+8
| | | | | | | | | | We forgot to add the status bit for the PLLs and we were using the wrong register and masks for configuration, leading to unexpected PLL configurations. Fix this. Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix clk_rcg2_is_enabled() checkStephen Boyd2014-05-291-1/+1
| | | | | | | | | If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic. Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: berlin: add core clock driver for BG2QAlexandre Belloni2014-05-292-0/+390
| | | | | | | | | This driver deals with the core clocks found on Marvell Berlin BG2Q. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: berlin: add core clock driver for BG2/BG2CDSebastian Hesselbarth2014-05-293-0/+722
| | | | | | | | | | | This driver deals with the core clocks found on Marvell Berlin BG2 and BG2CD. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: berlin: add driver for BG2x complex divider cellsAlexandre Belloni2014-05-293-1/+355
| | | | | | | | | | This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: berlin: add driver for BG2x simple PLLsAlexandre Belloni2014-05-293-1/+155
| | | | | | | | | | | This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: berlin: add driver for BG2x audio/video PLLSebastian Hesselbarth2014-05-294-0/+431
| | | | | | | | | | | | This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Terminate of match tableStephen Boyd2014-05-281-0/+1
| | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk/exynos4: Fix compilation warningSachin Kamat2014-05-281-2/+2
| | | | | | | | | | | | | Fixes the following warning: WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown) The function exynos4_clk_sleep_init() references the (unknown reference) __initdata (unknown). This is often because exynos4_clk_sleep_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-282-22/+46
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| * Merge tag 'clk-tegra-fixes-3.15' of ↵Mike Turquette2014-05-281-21/+43
| |\ | | | | | | | | | | | | | | | git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes PLLE fixes for 3.15
| | * clk: tegra: Fix enabling of PLLEThierry Reding2014-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: Introduce divider mask and shift helpersThierry Reding2014-04-171-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the code that modifies the m-, n- and p-divider fields of PLLs shorter and easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: Fix PLLE programmingThierry Reding2014-04-171-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a situation where the PLLE programming would only work if the register hadn't been touched before. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | clk: st: Fix memory leakValentin Ilie2014-05-241-1/+3
| | | | | | | | | | | | | | | | | | | | | When it fails to allocate div, gate should be free'd before return Signed-off-by: Valentin Ilie <valentin.ilie@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: divider: Fix overflow in clk_divider_bestdivTomasz Figa2014-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: u300: Terminate of match tableStephen Boyd2014-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: bcm/kona: implement determine_rate()Alex Elder2014-05-281-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: qcom: Fix blsp2_ahb_clk register offsetGeorgi Djakov2014-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: s2mps11: Add support for S2MPS14 clocksKrzysztof Kozlowski2014-05-242-20/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: s2mps11: Remove useless check for clk_tableKrzysztof Kozlowski2014-05-241-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for checking if 'clk_table' is not NULL twice (first after allocation and second at the end of probe()). Also move allocation of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is logical place for it. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: s2mps11: Add missing of_node_put and of_clk_del_providerKrzysztof Kozlowski2014-05-241-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add of_clk_del_provider to remove previously registered clock provider. Add of_node_put to decrement the ref count of clock nodes. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-231-1/+1
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| * | clk: divider: Fix table round up functionMaxime COQUELIN2014-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and table dividers") introduces a regression in its _table_round_up function. When the divider passed to this function is greater than the max divider available in the table, this function returns table's max divider. Problem is that it causes an infinite loop in clk_divider_bestdiv() because _next_div() will never return a value greater than maxdiv. Instead of returning table's max divider, this patch returns INT_MAX. Reported-by: Fabio Estevam <festevam@gmail.com> Reported-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <festevam@gmail.com> Tested-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | Merge remote-tracking branch 'linaro/clk-next' into clk-nextMike Turquette2014-05-2347-644/+2815
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| * | clk: Neaten clk_summary outputGeert Uytterhoeven2014-05-231-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner2014-05-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Max Schwarz <max.schwarz@online.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: shmobile: Add R8A7740-specific clock supportUlrich Hecht2014-05-232-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: tegra: Initialize xusb clocksAndrew Bresticker2014-05-232-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-234-20/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: tegra: Fix xusb_fs_src muxJim Lin2014-05-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: tegra: Enable hardware control of PLLEJim Lin2014-05-231-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: Add clock driver for AXM55xx SoCAnders Berg2014-05-232-0/+616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by: Anders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: shmobile: mstp: Fix the is_enabled() operationLaurent Pinchart2014-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: Add of_clk_get_by_clkspec() helperSylwester Nawrocki2014-05-232-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds of_clk_get_by_clkspec() helper function, which does only a struct clk lookup from the clock providers. It is used in the subsequent patch where parsing of a clock from device tree and the lookup from providers needed to be split. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: impd1: add pclk clocksLinus Walleij2014-05-221-7/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IM-PD1 PrimeCells all have pclk assignments though this clock cannot be controlled, and we need to provide this as a dummy clock for the PL061 GPIO driver to probe, so let's assign it to all the cells on the board. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | Merge tag 'zynq-clk-for-3.16' of git://git.xilinx.com/linux-xlnx into ↵Mike Turquette2014-05-212-1/+13
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next-zynq arm: Xilinx Zynq clk patches for v3.16 - Keep debug clocks in bootup state - Fix email address in si570
| | * | clk: si570: Fix email address specifictionMichal Simek2014-05-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Just fix missing ">" in the email. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | clk: zynq: Leave debug clocks in bootup stateSoren Brinkmann2014-04-221-0/+12
| | |/ | | | | | | | | | | | | | | | | | | | | | Make sure debug clocks stay enabled if the bootloader enabled them. Otherwise debug HW may crash due to bus-hangs caused by stopped clocks. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | clk: qcom: Fix msm8660 GCC probeStephen Boyd2014-05-171-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When consolidating the msm8660 GCC probe code I forgot to keep around these temporary clock registrations. Put them back so the clock tree is not entirely orphaned. Fixes: 49fc825f0cc2 (clk: qcom: Consolidate common probe code) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-171-1/+1
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| * | | clk/versatile: export symbols for impd1Arnd Bergmann2014-05-152-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The impd1 code on mach-integrator can be a loadable module, so we have to export icst_clk_register, integrator_impd1_clk_init and integrator_impd1_clk_exit. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | Merge tag 'clk-hisi-for-v3.16' of ↵Mike Turquette2014-05-155-5/+142
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon enable hix5hd2 clock
| | * | | clk: hisi: add clk-hix5hd2.cZhangfei Gao2014-05-123-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 00:41:51 +0100