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| * | | clk: imx: add gatable clock divider supportA.s. Dong2018-12-033-0/+226
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*-------. \ \ Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd2018-12-1447-232/+3116
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| | | | | * | | clk: rockchip: add clock-id to gate of ACODEC for rk3328Katsuhiro Suzuki2018-11-261-1/+1
| | | | | * | | clk: rockchip: fix I2S1 clock gate register for rk3328Katsuhiro Suzuki2018-11-191-1/+1
| | | | | * | | clk: rockchip: make rk3188 hclk_vio_bus criticalMark Yao2018-11-151-1/+2
| | | | | * | | clk: rockchip: fix rk3188 sclk_mac_lbtest parameter orderingHeiko Stuebner2018-11-151-2/+2
| | | | | * | | clk: rockchip: fix rk3188 sclk_smc gate dataFinley Xiao2018-11-151-2/+2
| | | | | * | | clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker2018-11-121-1/+1
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| | | | * | | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd2018-12-137-71/+870
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| | | | | * | | clk: meson: axg-audio: use the clk input helper functionJerome Brunet2018-12-111-59/+24
| | | | | * | | clk: meson: add clk-input helper functionJerome Brunet2018-12-053-0/+50
| | | | | * | | clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-032-10/+782
| | | | | * | | clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-032-0/+6
| | | | | * | | clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
| | | | | * | | clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong2018-11-271-1/+7
| | | | * | | | clk: meson: Mark some things staticStephen Boyd2018-12-032-6/+6
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| | | | * | | clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-232-1/+256
| | | | * | | clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-232-12/+12
| | | | * | | clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2018-11-232-0/+6
| | | | * | | clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
| | | | * | | clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
| | | | * | | clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
| | | | * | | clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
| | | | * | | clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
| | | | * | | clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl2018-11-231-0/+19
| | | | * | | clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
| | | | * | | clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
| | | | * | | clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
| | | | * | | clk: meson-gxbb: Add video clocksNeil Armstrong2018-11-231-0/+722
| | | | * | | dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong2018-11-231-2/+24
| | | | * | | clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong2018-11-231-2/+49
| | | | * | | clk: meson: Add vid_pll divider driverNeil Armstrong2018-11-233-1/+98
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| | | * | | clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang2018-12-141-3/+4
| | | * | | clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter2018-12-141-3/+3
| | | * | | soc/tegra: pmc: Drop SMP dependency from CPU APIsJon Hunter2018-12-141-2/+0
| | | * | | clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-147-13/+37
| | | * | | clk: tegra: get rid of duplicate definesMarcel Ziswiler2018-12-141-3/+0
| | | * | | clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko2018-11-081-0/+10
| | | * | | clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko2018-11-081-10/+26
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| | * | | clk: sunxi-ng: a64: Allow parent change for VE clockJernej Skrabec2018-12-101-1/+1
| | * | | clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai2018-12-051-3/+3
| | * | | clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLLChen-Yu Tsai2018-12-051-13/+24
| | * | | clk: sunxi-ng: h3: Allow parent change for ve clockJernej Skrabec2018-12-041-1/+1
| | * | | clk: sunxi-ng: add support for suniv F1C100s SoCMesih Kilinc2018-12-044-0/+581
| | * | | clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai2018-12-031-1/+1
| | * | | clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC outputChen-Yu Tsai2018-11-301-0/+11
| | * | | clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLLChen-Yu Tsai2018-11-231-13/+24
| | * | | clk: sunxi-ng: a64: Fix gate bit of DSI DPHYJagan Teki2018-11-131-1/+1
| | * | | clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50IJagan Teki2018-11-131-0/+1
| | * | | clk: sunxi-ng: Add support for H6 DE3 clocksJernej Skrabec2018-11-052-4/+71
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